From mboxrd@z Thu Jan 1 00:00:00 1970 From: Tom Rini Date: Tue, 19 Jan 2021 15:01:32 -0500 Subject: [PATCH V3] net: dwc_eth_qos: Pad descriptors to cacheline size In-Reply-To: <20210107101216.5545-1-marex@denx.de> References: <20210107101216.5545-1-marex@denx.de> Message-ID: <20210119200132.GT9782@bill-the-cat> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On Thu, Jan 07, 2021 at 11:12:16AM +0100, Marek Vasut wrote: > The DWMAC4 IP has the possibility to skip up to 7 AXI bus width size words > after the descriptor. Use this to pad the descriptors to cacheline size and > remove the need for noncached memory altogether. Moreover, this lets Tegra > use the generic cache flush / invalidate operations. > > Signed-off-by: Marek Vasut > Cc: Joe Hershberger > Cc: Patrice Chotard > Cc: Patrick Delaunay > Cc: Ramon Fried > Cc: Stephen Warren > Tested-by: Stephen Warren > Reviewed-by: Stephen Warren > Tested-by: Patrice Chotard Applied to u-boot/master, thanks! -- Tom -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 659 bytes Desc: not available URL: