From: Bin Meng <bmeng.cn@gmail.com>
To: u-boot@lists.denx.de
Subject: [PATCH 1/7] riscv: Adjust board_get_usable_ram_top() for 32-bit
Date: Thu, 21 Jan 2021 23:00:09 +0800 [thread overview]
Message-ID: <20210121150015.25558-2-bmeng.cn@gmail.com> (raw)
In-Reply-To: <20210121150015.25558-1-bmeng.cn@gmail.com>
From: Bin Meng <bin.meng@windriver.com>
When testing QEMU RISC-V 'virt' machine with a 2 GiB memory
configuration, it was discovered gd->ram_top is assigned to
value zero in setup_dest_addr().
While gd->ram_top should not be declared as type `unsigned long`,
which will be updated in a future patch, the current logic in
board_get_usable_ram_top() can be updated to cover both 64-bit
and 32-bit RISC-V.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
---
arch/riscv/cpu/fu540/dram.c | 7 +++----
arch/riscv/cpu/generic/dram.c | 7 +++----
2 files changed, 6 insertions(+), 8 deletions(-)
diff --git a/arch/riscv/cpu/fu540/dram.c b/arch/riscv/cpu/fu540/dram.c
index 1dc77efeca..259da65a54 100644
--- a/arch/riscv/cpu/fu540/dram.c
+++ b/arch/riscv/cpu/fu540/dram.c
@@ -22,7 +22,6 @@ int dram_init_banksize(void)
ulong board_get_usable_ram_top(ulong total_size)
{
-#ifdef CONFIG_64BIT
/*
* Ensure that we run from first 4GB so that all
* addresses used by U-Boot are 32bit addresses.
@@ -31,8 +30,8 @@ ulong board_get_usable_ram_top(ulong total_size)
* devices work fine because DMA mapping APIs will
* provide 32bit DMA addresses only.
*/
- if (gd->ram_top > SZ_4G)
- return SZ_4G;
-#endif
+ if (gd->ram_top >= SZ_4G)
+ return SZ_4G - 1;
+
return gd->ram_top;
}
diff --git a/arch/riscv/cpu/generic/dram.c b/arch/riscv/cpu/generic/dram.c
index 1dc77efeca..259da65a54 100644
--- a/arch/riscv/cpu/generic/dram.c
+++ b/arch/riscv/cpu/generic/dram.c
@@ -22,7 +22,6 @@ int dram_init_banksize(void)
ulong board_get_usable_ram_top(ulong total_size)
{
-#ifdef CONFIG_64BIT
/*
* Ensure that we run from first 4GB so that all
* addresses used by U-Boot are 32bit addresses.
@@ -31,8 +30,8 @@ ulong board_get_usable_ram_top(ulong total_size)
* devices work fine because DMA mapping APIs will
* provide 32bit DMA addresses only.
*/
- if (gd->ram_top > SZ_4G)
- return SZ_4G;
-#endif
+ if (gd->ram_top >= SZ_4G)
+ return SZ_4G - 1;
+
return gd->ram_top;
}
--
2.25.1
next prev parent reply other threads:[~2021-01-21 15:00 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-01-21 15:00 [PATCH 0/7] Allow booting a 32-bit system with a top memory address beyond 4 GiB Bin Meng
2021-01-21 15:00 ` Bin Meng [this message]
2021-01-21 15:00 ` [PATCH 2/7] global_data.h: Change ram_top type to phys_addr_t Bin Meng
2021-01-24 2:03 ` Simon Glass
2021-01-29 17:47 ` Simon Glass
2021-01-30 10:13 ` Bin Meng
2021-01-30 16:24 ` Simon Glass
2021-01-31 3:40 ` Bin Meng
2021-01-31 3:44 ` Simon Glass
2021-01-31 8:35 ` Bin Meng
2021-01-21 15:00 ` [PATCH 3/7] serial: sifive: Cast dev_read_addr() with uintptr_t Bin Meng
2021-01-21 15:00 ` [PATCH 4/7] fdtdec: Cast prior_stage_fdt_address " Bin Meng
2021-01-24 2:03 ` Simon Glass
2021-01-21 15:00 ` [PATCH 5/7] riscv: Change phys_addr_t and phys_size_t to 64-bit Bin Meng
2021-01-21 15:00 ` [PATCH 6/7] bdinfo: Rename function names to be clearer Bin Meng
2021-01-21 15:00 ` [PATCH 7/7] bdinfo: Change to use bdinfo_print_num_ll() where the number could be 64-bit Bin Meng
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