[PATCH 1/4] arm: a37xx: pci: Set Max Payload Size and Max Read Request Size to 512 bytes

["Pali Rohár" <pali@kernel.org>]

Fix usage of VL805 XHCI PCIe controller when it is connected via PCIe to
Armada 3720 SOC. Without this U-Boot crashes when trying to access
enumerated USB devices connected to this XHCI PCIe controller.

This should be done according to the PCIe Link Initialization sequence, as
defined in Marvell Armada 3720 Functional Specification.

Linux has this code too.

Signed-off-by: Pali Roh?r <pali@kernel.org>
---
 drivers/pci/pci-aardvark.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/drivers/pci/pci-aardvark.c b/drivers/pci/pci-aardvark.c
index 8713b88461..b4e1b60240 100644
--- a/drivers/pci/pci-aardvark.c
+++ b/drivers/pci/pci-aardvark.c
@@ -42,6 +42,10 @@
 #define PCIE_CORE_DEV_CTRL_STATS_REG				0xc8
 #define     PCIE_CORE_DEV_CTRL_STATS_RELAX_ORDER_DISABLE	(0 << 4)
 #define     PCIE_CORE_DEV_CTRL_STATS_SNOOP_DISABLE		(0 << 11)
+#define     PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SIZE		0x2
+#define     PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SIZE_SHIFT	5
+#define     PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE		0x2
+#define     PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE_SHIFT	12
 #define PCIE_CORE_LINK_CTRL_STAT_REG				0xd0
 #define     PCIE_CORE_LINK_TRAINING				BIT(5)
 #define PCIE_CORE_ERR_CAPCTL_REG				0x118
@@ -534,6 +538,10 @@ static int pcie_advk_setup_hw(struct pcie_advk *pcie)
 
 	/* Set PCIe Device Control and Status 1 PF0 register */
 	reg = PCIE_CORE_DEV_CTRL_STATS_RELAX_ORDER_DISABLE |
+		(PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SIZE <<
+		 PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SIZE_SHIFT) |
+		(PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE <<
+		 PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE_SHIFT) |
 		PCIE_CORE_DEV_CTRL_STATS_SNOOP_DISABLE;
 	advk_writel(pcie, reg, PCIE_CORE_DEV_CTRL_STATS_REG);
 
-- 
2.20.1