From mboxrd@z Thu Jan 1 00:00:00 1970 From: Leo Liang Date: Fri, 26 Feb 2021 09:53:24 +0800 Subject: [GIT PULL] u-boot-riscv/master Message-ID: <20210226015324.GA26044@andestech.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de Hi Tom, Please pull some RISC-V updates. CI result: https://gitlab.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/6505 The following changes since commit cbe607b920bc0827d8fe379ed4f5ae4e2058513e: Merge tag 'xilinx-for-v2021.04-rc3' of https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze (2021-02-23 10:45:55 -0500) are available in the Git repository at: git at gitlab.denx.de:u-boot/custodians/u-boot-riscv.git for you to fetch changes up to 5540294fa48598bf1aa8aa4d9084506a19bbd64c: riscv: k210: Enable QSPI for spi3 (2021-02-25 18:06:08 +0800) ---------------------------------------------------------------- Heinrich Schuchardt (1): cmd/riscv/sbi: support System Reset Extension Sean Anderson (1): riscv: k210: Enable QSPI for spi3 arch/riscv/dts/k210-maix-bit.dts | 2 ++ cmd/riscv/sbi.c | 1 + 2 files changed, 3 insertions(+) Best regards, Leo