From mboxrd@z Thu Jan  1 00:00:00 1970
From: Arnaud Patard (Rtp) <arnaud.patard@rtp-net.org>
Date: Fri, 05 Mar 2021 11:27:48 +0100
Subject: [patch v4 3/9] Rockchip: video: edp: Change interrupt polarity
 configuration
References: <20210305102745.078091129@rtp-net.org>
Message-ID: <20210305103307.112947687@rtp-net.org>
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To: u-boot@lists.denx.de

The linux code is setting polarity configuration to 3 but
uboot code is setting it to 1. Change the configuration to match the
linux configuration

Signed-off-by: Arnaud Patard <arnaud.patard@rtp-net.org>
Tested-by: Peter Robinson <pbrobinson@gmail.com>
Index: u-boot/arch/arm/include/asm/arch-rockchip/edp_rk3288.h
===================================================================
--- u-boot.orig/arch/arm/include/asm/arch-rockchip/edp_rk3288.h
+++ u-boot/arch/arm/include/asm/arch-rockchip/edp_rk3288.h
@@ -297,7 +297,9 @@ check_member(rk3288_edp, pll_reg_5, 0xa0
 
 /* int_ctl */
 #define SOFT_INT_CTRL				(0x1 << 2)
-#define INT_POL					(0x1 << 0)
+#define INT_POL1				(0x1 << 1)
+#define INT_POL0				(0x1 << 0)
+#define INT_POL					(INT_POL0 | INT_POL1)
 
 /* sys_ctl_1 */
 #define DET_STA					(0x1 << 2)