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From: Jagan Teki <jagan@amarulasolutions.com>
To: u-boot@lists.denx.de
Subject: [PATCH v3 6/8] ARM: dts: stm32: Add Engicam MicroGEA STM32MP1 Micro SoM
Date: Tue, 16 Mar 2021 21:52:05 +0530	[thread overview]
Message-ID: <20210316162207.35641-7-jagan@amarulasolutions.com> (raw)
In-Reply-To: <20210316162207.35641-1-jagan@amarulasolutions.com>

MicroGEA STM32MP1 is a STM32MP157A based Micro SoM.

General features:
- STM32MP157AAC
- Up to 1GB DDR3L-800
- 512MB Nand flash
- I2S

MicroGEA STM32MP1 needs to mount on top of Engicam MicroDev carrier
boards for creating complete platform solutions.

Linux dts commit details:

commit <0be81dfaeaf8> ("ARM: dts: stm32: Add Engicam MicroGEA STM32MP1
SoM")

Add support for it.

Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
Changes for v3:
- collect Patrice r-b
Changes for v2:
- collect Patrice r-b
- add linux dts commit
- drop CONFIG_BOARD_EARLY_INIT_F

 .../dts/stm32mp157a-microgea-stm32mp1.dtsi    | 148 ++++++++++++++++++
 1 file changed, 148 insertions(+)
 create mode 100644 arch/arm/dts/stm32mp157a-microgea-stm32mp1.dtsi

diff --git a/arch/arm/dts/stm32mp157a-microgea-stm32mp1.dtsi b/arch/arm/dts/stm32mp157a-microgea-stm32mp1.dtsi
new file mode 100644
index 0000000000..0b85175f15
--- /dev/null
+++ b/arch/arm/dts/stm32mp157a-microgea-stm32mp1.dtsi
@@ -0,0 +1,148 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (c) STMicroelectronics 2019 - All Rights Reserved
+ * Copyright (c) 2020 Engicam srl
+ * Copyright (c) 2020 Amarula Solutons(India)
+ */
+
+/ {
+	compatible = "engicam,microgea-stm32mp1", "st,stm32mp157";
+
+	memory at c0000000 {
+		device_type = "memory";
+		reg = <0xc0000000 0x10000000>;
+	};
+
+	reserved-memory {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		mcuram2: mcuram2 at 10000000 {
+			compatible = "shared-dma-pool";
+			reg = <0x10000000 0x40000>;
+			no-map;
+		};
+
+		vdev0vring0: vdev0vring0 at 10040000 {
+			compatible = "shared-dma-pool";
+			reg = <0x10040000 0x1000>;
+			no-map;
+		};
+
+		vdev0vring1: vdev0vring1 at 10041000 {
+			compatible = "shared-dma-pool";
+			reg = <0x10041000 0x1000>;
+			no-map;
+		};
+
+		vdev0buffer: vdev0buffer at 10042000 {
+			compatible = "shared-dma-pool";
+			reg = <0x10042000 0x4000>;
+			no-map;
+		};
+
+		mcuram: mcuram at 30000000 {
+			compatible = "shared-dma-pool";
+			reg = <0x30000000 0x40000>;
+			no-map;
+		};
+
+		retram: retram at 38000000 {
+			compatible = "shared-dma-pool";
+			reg = <0x38000000 0x10000>;
+			no-map;
+		};
+	};
+
+	vin: regulator-vin {
+		compatible = "regulator-fixed";
+		regulator-name = "vin";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		regulator-always-on;
+	};
+
+	vddcore: regulator-vddcore {
+		compatible = "regulator-fixed";
+		regulator-name = "vddcore";
+		regulator-min-microvolt = <1200000>;
+		regulator-max-microvolt = <1200000>;
+		regulator-always-on;
+		vin-supply = <&vin>;
+	};
+
+	vdd: regulator-vdd {
+		compatible = "regulator-fixed";
+		regulator-name = "vdd";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-always-on;
+		vin-supply = <&vin>;
+	};
+
+	vddq_ddr: regulator-vddq-ddr {
+		compatible = "regulator-fixed";
+		regulator-name = "vddq_ddr";
+		regulator-min-microvolt = <1350000>;
+		regulator-max-microvolt = <1350000>;
+		regulator-always-on;
+		vin-supply = <&vin>;
+	};
+};
+
+&dts {
+	status = "okay";
+};
+
+&fmc {
+	pinctrl-names = "default", "sleep";
+	pinctrl-0 = <&fmc_pins_a>;
+	pinctrl-1 = <&fmc_sleep_pins_a>;
+	status = "okay";
+
+	nand-controller at 4,0 {
+		status = "okay";
+
+		nand at 0 {
+			reg = <0>;
+			nand-on-flash-bbt;
+			#address-cells = <1>;
+			#size-cells = <1>;
+		};
+	};
+};
+
+&ipcc {
+	status = "okay";
+};
+
+&iwdg2{
+	timeout-sec = <32>;
+	status = "okay";
+};
+
+&m4_rproc{
+	memory-region = <&retram>, <&mcuram>, <&mcuram2>, <&vdev0vring0>,
+			<&vdev0vring1>, <&vdev0buffer>;
+	mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>;
+	mbox-names = "vq0", "vq1", "shutdown";
+	interrupt-parent = <&exti>;
+	interrupts = <68 1>;
+	status = "okay";
+};
+
+&rng1 {
+	status = "okay";
+};
+
+&rtc{
+	status = "okay";
+};
+
+&vrefbuf {
+	regulator-min-microvolt = <2500000>;
+	regulator-max-microvolt = <2500000>;
+	vdda-supply = <&vdd>;
+	status = "okay";
+};
-- 
2.25.1

  parent reply	other threads:[~2021-03-16 16:22 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-03-16 16:21 [PATCH v3 0/8] stm32: Add Engicam STM32MP1 SoM Jagan Teki
2021-03-16 16:22 ` [PATCH v3 1/8] ARM: dts: stm32: Add Engicam i.Core " Jagan Teki
2021-04-09  9:54   ` Patrice CHOTARD
2021-03-16 16:22 ` [PATCH v3 2/8] ARM: dts: stm32: Add Engicam i.Core STM32MP1 1X4Gb DDR3 Jagan Teki
2021-04-09  9:54   ` Patrice CHOTARD
2021-03-16 16:22 ` [PATCH v3 3/8] ARM: stm32: Imply SPL_SPI_LOAD Jagan Teki
2021-04-09  9:54   ` Patrice CHOTARD
2021-03-16 16:22 ` [PATCH v3 4/8] board: stm32: Add Engicam i.Core STM32MP1 EDIMM2.2 Starter Kit Jagan Teki
2021-04-09  9:54   ` Patrice CHOTARD
2021-03-16 16:22 ` [PATCH v3 5/8] board: stm32: Add Engicam i.Core STM32MP1 C.TOUCH 2.0 Jagan Teki
2021-04-09  9:55   ` Patrice CHOTARD
2021-03-16 16:22 ` Jagan Teki [this message]
2021-04-09  9:55   ` [PATCH v3 6/8] ARM: dts: stm32: Add Engicam MicroGEA STM32MP1 Micro SoM Patrice CHOTARD
2021-03-16 16:22 ` [PATCH v3 7/8] board: stm32: Add Engicam MicroGEA STM32MP1 MicroDev 2.0 board Jagan Teki
2021-04-09  9:55   ` Patrice CHOTARD
2021-03-16 16:22 ` [PATCH v3 8/8] board: stm32: Add Engicam MicroGEA STM32MP1 MicroDev 2.0 7" OF Jagan Teki
2021-04-09  9:55   ` Patrice CHOTARD

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