From mboxrd@z Thu Jan  1 00:00:00 1970
From: Andre Przywara <andre.przywara@arm.com>
Date: Sun, 28 Mar 2021 23:51:27 +0100
Subject: [PATCH 1/6] clk: sunxi: Add a dummy clock driver for the RTC
In-Reply-To: <20210208055724.58673-2-samuel@sholland.org>
References: <20210208055724.58673-1-samuel@sholland.org>
 <20210208055724.58673-2-samuel@sholland.org>
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On Sun,  7 Feb 2021 23:57:19 -0600
Samuel Holland <samuel@sholland.org> wrote:

> The 32kHz clock ("LOSC") on sunxi SoCs is provided by the RTC. It is
> used, among other things, by the XHCI controller in the H6. To be able
> to call clk_get_bulk() on the XHCI controller, some device needs to
> provide all referenced clocks.
> 
> Since LOSC is a fixed-rate always-on clock, implementation is trivial.
> 
> Signed-off-by: Samuel Holland <samuel@sholland.org>

Reviewed-by: Andre Przywara <andre.przywara@arm.com>

Queued for sunxi-next.

Cheers,
Andre


> ---
>  drivers/clk/sunxi/Makefile        |  2 ++
>  drivers/clk/sunxi/clk_sun6i_rtc.c | 35 +++++++++++++++++++++++++++++++
>  2 files changed, 37 insertions(+)
>  create mode 100644 drivers/clk/sunxi/clk_sun6i_rtc.c
> 
> diff --git a/drivers/clk/sunxi/Makefile b/drivers/clk/sunxi/Makefile
> index 0dfc0593fb1..4f9282a8b9b 100644
> --- a/drivers/clk/sunxi/Makefile
> +++ b/drivers/clk/sunxi/Makefile
> @@ -6,6 +6,8 @@
>  
>  obj-$(CONFIG_CLK_SUNXI) += clk_sunxi.o
>  
> +obj-$(CONFIG_CLK_SUNXI) += clk_sun6i_rtc.o
> +
>  obj-$(CONFIG_CLK_SUN4I_A10) += clk_a10.o
>  obj-$(CONFIG_CLK_SUN5I_A10S) += clk_a10s.o
>  obj-$(CONFIG_CLK_SUN6I_A31) += clk_a31.o
> diff --git a/drivers/clk/sunxi/clk_sun6i_rtc.c b/drivers/clk/sunxi/clk_sun6i_rtc.c
> new file mode 100644
> index 00000000000..0c280d221ba
> --- /dev/null
> +++ b/drivers/clk/sunxi/clk_sun6i_rtc.c
> @@ -0,0 +1,35 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright (C) 2018 Amarula Solutions.
> + * Copyright (C) 2020 Samuel Holland <samuel@sholland.org>
> + */
> +
> +#include <clk-uclass.h>
> +#include <dm.h>
> +
> +static int clk_sun6i_rtc_enable(struct clk *clk)
> +{
> +	return 0;
> +}
> +
> +static const struct clk_ops clk_sun6i_rtc_ops = {
> +	.enable = clk_sun6i_rtc_enable,
> +};
> +
> +static const struct udevice_id sun6i_rtc_ids[] = {
> +	{ .compatible = "allwinner,sun6i-a31-rtc" },
> +	{ .compatible = "allwinner,sun8i-a23-rtc" },
> +	{ .compatible = "allwinner,sun8i-h3-rtc" },
> +	{ .compatible = "allwinner,sun8i-r40-rtc" },
> +	{ .compatible = "allwinner,sun8i-v3-rtc" },
> +	{ .compatible = "allwinner,sun50i-h5-rtc" },
> +	{ .compatible = "allwinner,sun50i-h6-rtc" },
> +	{ }
> +};
> +
> +U_BOOT_DRIVER(clk_sun6i_rtc) = {
> +	.name		= "clk_sun6i_rtc",
> +	.id		= UCLASS_CLK,
> +	.of_match	= sun6i_rtc_ids,
> +	.ops		= &clk_sun6i_rtc_ops,
> +};