From mboxrd@z Thu Jan 1 00:00:00 1970 From: Pratyush Yadav Date: Fri, 2 Apr 2021 01:01:26 +0530 Subject: [PATCH v8 21/28] mtd: spi-nor-core: Do not make invalid quad enable fatal In-Reply-To: <20210401193133.18129-1-p.yadav@ti.com> References: <20210401193133.18129-1-p.yadav@ti.com> Message-ID: <20210401193133.18129-22-p.yadav@ti.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de The Micron MT35XU512ABA flash does not support the quad enable bit. But instead of programming the Quad Enable Require field to 000b ("Device does not have a QE bit"), it is programmed to 111b ("Reserved"). While this is technically incorrect, it is not reason enough to abort BFPT parsing. Instead, continue BFPT parsing assuming there is no quad enable bit present. Signed-off-by: Pratyush Yadav --- drivers/mtd/spi/spi-nor-core.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c index cf0694bca3..2c131bc0f8 100644 --- a/drivers/mtd/spi/spi-nor-core.c +++ b/drivers/mtd/spi/spi-nor-core.c @@ -2100,7 +2100,8 @@ static int spi_nor_parse_bfpt(struct spi_nor *nor, break; #endif default: - return -EINVAL; + dev_dbg(nor->dev, "BFPT QER reserved value used\n"); + break; } /* Stop here if JESD216 rev B. */ -- 2.30.0