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From: Sean Anderson <seanga2@gmail.com>
To: u-boot@lists.denx.de
Subject: [PATCH v3 00/11] riscv: k210: Enable use of AI ram bank
Date: Thu,  8 Apr 2021 22:13:02 -0400	[thread overview]
Message-ID: <20210409021313.433558-1-seanga2@gmail.com> (raw)

This ram bank was previously unusable because PLL1 was not started correctly.
This series fixes that bug, and allows U-Boot to relocate into the AI ram. This
provides an extra 2M of space in which to load payloads.  I've also added some
minor patches to bring the device tree and clock driver closer to what Linux has
(or will have).

The bypass clock turned out to be still necessary after all; I had neglected to
test with CLK_K210_SET_RATE enabled, and I didn't notice that the clock rate
wasn't actually getting set (oops). I've added a warning which will hopefully
make it more difficult to make such mistakes in the future.

Changes in v3:
- Add a warning if we can't assign rates
- Split off patchs for fdtdec_setup_mem_size_base_* into another series
- Eliminated separate RAM driver
- Rebased onto u-boot/next

Changes in v2:
- Don't re-enable the PLL
- Simplify PLL instantiation
- Modify clock tree so clint is a child of aclk
- Sync memory dts node with Linux
- Use correct aisram clock

Sean Anderson (11):
  clk: Warn on failure to assign rate
  clk: k210: Fix PLLs not being enabled
  clk: k210: Fix PLL enable always getting taken
  clk: k210: Remove k210_register_pll
  clk: k210: Move the clint clock to under aclk
  clk: Add support for the k210 clock driver pre-relocation
  riscv: Enable some devices pre-relocation
  riscv: Enable AI ram on K210
  riscv: k210: Rename airam to aisram
  riscv: k210: Use AI as the parent clock of aisram, not PLL1
  riscv: Don't reserve AI ram in k210 dts

 arch/riscv/dts/k210.dtsi           | 22 +++++++---------------
 board/sipeed/maix/maix.c           | 14 ++++++++++++--
 configs/sipeed_maix_bitm_defconfig |  2 ++
 drivers/clk/clk-uclass.c           | 11 +++++++----
 drivers/clk/kendryte/clk.c         | 26 ++++++++++++++------------
 drivers/clk/kendryte/pll.c         | 26 ++++----------------------
 include/configs/sipeed-maix.h      |  3 +--
 include/kendryte/pll.h             |  4 ----
 8 files changed, 47 insertions(+), 61 deletions(-)

-- 
2.31.0

             reply	other threads:[~2021-04-09  2:13 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-04-09  2:13 Sean Anderson [this message]
2021-04-09  2:13 ` [PATCH v3 01/11] clk: Warn on failure to assign rate Sean Anderson
2021-04-09  2:13 ` [PATCH v3 02/11] clk: k210: Fix PLLs not being enabled Sean Anderson
2021-04-09  2:45   ` Damien Le Moal
2021-04-09  2:13 ` [PATCH v3 03/11] clk: k210: Fix PLL enable always getting taken Sean Anderson
2021-04-09  2:13 ` [PATCH v3 04/11] clk: k210: Remove k210_register_pll Sean Anderson
2021-04-09  2:13 ` [PATCH v3 05/11] clk: k210: Move the clint clock to under aclk Sean Anderson
2021-04-09  2:54   ` Damien Le Moal
2021-04-09  2:57     ` Sean Anderson
2021-04-09  3:00       ` Damien Le Moal
2021-04-09  2:58     ` Damien Le Moal
2021-04-09  3:09       ` Sean Anderson
2021-04-09  2:13 ` [PATCH v3 06/11] clk: Add support for the k210 clock driver pre-relocation Sean Anderson
2021-04-09  2:13 ` [PATCH v3 07/11] riscv: Enable some devices pre-relocation Sean Anderson
2021-04-09  2:13 ` [PATCH v3 08/11] riscv: Enable AI ram on K210 Sean Anderson
2021-04-09  2:13 ` [PATCH v3 09/11] riscv: k210: Rename airam to aisram Sean Anderson
2021-04-09  2:13 ` [PATCH v3 10/11] riscv: k210: Use AI as the parent clock of aisram, not PLL1 Sean Anderson
2021-04-09  2:13 ` [PATCH v3 11/11] riscv: Don't reserve AI ram in k210 dts Sean Anderson

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