From mboxrd@z Thu Jan 1 00:00:00 1970 From: Sean Anderson Date: Thu, 8 Apr 2021 22:13:05 -0400 Subject: [PATCH v3 03/11] clk: k210: Fix PLL enable always getting taken In-Reply-To: <20210409021313.433558-1-seanga2@gmail.com> References: <20210409021313.433558-1-seanga2@gmail.com> Message-ID: <20210409021313.433558-4-seanga2@gmail.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de This conditional always evaluated as false, regardless of the value of reg. Fix it so that it properly tests the bits in the PLL register. Also test PLL_EN, now that we set it. Reported-by: Damien Le Moal Signed-off-by: Sean Anderson --- (no changes since v2) Changes in v2: - New drivers/clk/kendryte/pll.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/clk/kendryte/pll.c b/drivers/clk/kendryte/pll.c index f198920113..d46fd0ebbf 100644 --- a/drivers/clk/kendryte/pll.c +++ b/drivers/clk/kendryte/pll.c @@ -512,7 +512,8 @@ static int k210_pll_enable(struct clk *clk) struct k210_pll *pll = to_k210_pll(clk); u32 reg = readl(pll->reg); - if ((reg | K210_PLL_PWRD) && !(reg | K210_PLL_RESET)) + if ((reg & K210_PLL_PWRD) && (reg & K210_PLL_EN) && + !(reg & K210_PLL_RESET)) return 0; reg |= K210_PLL_PWRD; -- 2.31.0