From: Sean Anderson <seanga2@gmail.com>
To: u-boot@lists.denx.de
Subject: [PATCH 04/11] clk: k210: Implement soc_clk_dump
Date: Sun, 11 Apr 2021 23:58:00 -0400 [thread overview]
Message-ID: <20210412035807.708621-5-seanga2@gmail.com> (raw)
In-Reply-To: <20210412035807.708621-1-seanga2@gmail.com>
Since we are no longer using CCF we cannot use the default soc_clk_dump.
Instead, implement our own.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
---
drivers/clk/kendryte/clk.c | 68 ++++++++++++++++++++++++++++++++++++--
1 file changed, 66 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/kendryte/clk.c b/drivers/clk/kendryte/clk.c
index de9db84361..203d5f741c 100644
--- a/drivers/clk/kendryte/clk.c
+++ b/drivers/clk/kendryte/clk.c
@@ -925,14 +925,19 @@ static void k210_pll_waitfor_lock(struct k210_clk_priv *priv, int id)
}
}
+static bool k210_pll_enabled(u32 reg)
+{
+ return (reg & K210_PLL_PWRD) && (reg & K210_PLL_EN) &&
+ !(reg & K210_PLL_RESET);
+}
+
/* Adapted from sysctl_pll_enable */
static int k210_pll_enable(struct k210_clk_priv *priv, int id)
{
const struct k210_pll_params *pll = &k210_plls[id];
u32 reg = readl(priv->base + pll->off);
- if ((reg & K210_PLL_PWRD) && (reg & K210_PLL_EN) &&
- !(reg & K210_PLL_RESET))
+ if (k210_pll_enabled(reg))
return 0;
reg |= K210_PLL_PWRD;
@@ -1174,3 +1179,62 @@ U_BOOT_DRIVER(k210_clk) = {
.probe = k210_clk_probe,
.priv_auto = sizeof(struct k210_clk_priv),
};
+
+#if CONFIG_IS_ENABLED(CMD_CLK)
+static char show_enabled(struct k210_clk_priv *priv, int id)
+{
+ bool enabled;
+
+ if (k210_clks[id].flags & K210_CLKF_PLL) {
+ const struct k210_pll_params *pll =
+ &k210_plls[k210_clks[id].pll];
+
+ enabled = k210_pll_enabled(readl(priv->base + pll->off));
+ } else if (k210_clks[id].gate == K210_CLK_GATE_NONE) {
+ return '-';
+ } else {
+ const struct k210_gate_params *gate =
+ &k210_gates[k210_clks[id].gate];
+
+ enabled = k210_clk_readl(priv, gate->off, gate->bit_idx, 1);
+ }
+
+ return enabled ? 'y' : 'n';
+}
+
+static void show_clks(struct k210_clk_priv *priv, int id, int depth)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(k210_clks); i++) {
+ if (k210_clk_get_parent(priv, i) != id)
+ continue;
+
+ printf(" %-9lu %-7c %*s%s\n", do_k210_clk_get_rate(priv, i),
+ show_enabled(priv, i), depth * 4, "",
+ k210_clks[i].name);
+
+ show_clks(priv, i, depth + 1);
+ }
+}
+
+int soc_clk_dump(void)
+{
+ int ret;
+ struct udevice *dev;
+ struct k210_clk_priv *priv;
+
+ ret = uclass_get_device_by_driver(UCLASS_CLK, DM_DRIVER_GET(k210_clk),
+ &dev);
+ if (ret)
+ return ret;
+ priv = dev_get_priv(dev);
+
+ puts(" Rate Enabled Name\n");
+ puts("------------------------\n");
+ printf(" %-9lu %-7c %*s%s\n", clk_get_rate(&priv->in0), 'y', 0, "",
+ priv->in0.dev->name);
+ show_clks(priv, K210_CLK_IN0, 1);
+ return 0;
+}
+#endif
--
2.31.0
next prev parent reply other threads:[~2021-04-12 3:58 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-04-12 3:57 [PATCH 00/11] clk: k210: Rewrite K210 clock without CCF Sean Anderson
2021-04-12 3:57 ` [PATCH 01/11] clk: Allow force setting clock defaults before relocation Sean Anderson
2021-04-14 19:38 ` Simon Glass
2021-05-10 7:06 ` Leo Liang
2021-04-12 3:57 ` [PATCH 02/11] clk: k210: Rewrite to remove CCF Sean Anderson
2021-04-12 3:57 ` [PATCH 03/11] clk: k210: Move pll into the rest of the driver Sean Anderson
2021-04-12 3:58 ` Sean Anderson [this message]
2021-04-12 3:58 ` [PATCH 05/11] clk: k210: Re-add support for setting rate Sean Anderson
2021-04-12 3:58 ` [PATCH 06/11] clk: k210: Don't set PLL rates if we are already at the correct rate Sean Anderson
2021-04-12 3:58 ` [PATCH 07/11] clk: k210: Remove bypass driver Sean Anderson
2021-04-12 3:58 ` [PATCH 08/11] clk: k210: Move k210 clock out of its own subdirectory Sean Anderson
2021-04-12 3:58 ` [PATCH 09/11] k210: dts: Set PLL1 to the same rate as PLL0 Sean Anderson
2021-04-12 3:58 ` [PATCH 10/11] k210: Don't imply CCF Sean Anderson
2021-04-12 3:58 ` [PATCH 11/11] test: Add K210 PLL tests to sandbox defconfigs Sean Anderson
2021-04-14 19:38 ` Simon Glass
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