[PATCH 06/27] mips: Remove malta boards

Tom Rini
2021-05-15T01:34:11Z

These boards have not been converted to CONFIG_DM_PCI by the deadline.
Remove them.

Cc: Paul Burton <paul.burton@mips.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
---
As I hope these boards will get converted quickly I've not removed all
of the other references to Malta and the associated PCI host controller
drivers.
---
arch/mips/Kconfig | 1 -
board/imgtec/malta/Kconfig | 16 --
board/imgtec/malta/MAINTAINERS | 9 -
board/imgtec/malta/Makefile | 8 -
board/imgtec/malta/flash-malta-boot.tcl | 38 ----
board/imgtec/malta/lowlevel_init.S | 231 -----------------------
board/imgtec/malta/malta.c | 233 ------------------------
board/imgtec/malta/superio.c | 62 -------
board/imgtec/malta/superio.h | 14 --
configs/malta64_defconfig | 33 ----
configs/malta64el_defconfig | 35 ----
configs/malta_defconfig | 32 ----
configs/maltael_defconfig | 34 ----
include/configs/malta.h | 81 --------
14 files changed, 827 deletions(-)
delete mode 100644 board/imgtec/malta/Kconfig
delete mode 100644 board/imgtec/malta/MAINTAINERS
delete mode 100644 board/imgtec/malta/Makefile
delete mode 100644 board/imgtec/malta/flash-malta-boot.tcl
delete mode 100644 board/imgtec/malta/lowlevel_init.S
delete mode 100644 board/imgtec/malta/malta.c
delete mode 100644 board/imgtec/malta/superio.c
delete mode 100644 board/imgtec/malta/superio.h
delete mode 100644 configs/malta64_defconfig
delete mode 100644 configs/malta64el_defconfig
delete mode 100644 configs/malta_defconfig
delete mode 100644 configs/maltael_defconfig
delete mode 100644 include/configs/malta.h

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 77f563e98ed2..dc13c8c6ce6a 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -172,7 +172,6 @@ config TARGET_XILFPGA
endchoice

source "board/imgtec/boston/Kconfig"
-source "board/imgtec/malta/Kconfig"
source "board/imgtec/xilfpga/Kconfig"
source "board/qemu-mips/Kconfig"
source "arch/mips/mach-ath79/Kconfig"
diff --git a/board/imgtec/malta/Kconfig b/board/imgtec/malta/Kconfig
deleted file mode 100644
index 98eb4d16c717..000000000000
--- a/board/imgtec/malta/Kconfig
+++ /dev/null
@@ -1,16 +0,0 @@
-if TARGET_MALTA
-
-config SYS_BOARD
- default "malta"
-
-config SYS_VENDOR
- default "imgtec"
-
-config SYS_CONFIG_NAME
- default "malta"
-
-config SYS_TEXT_BASE
- default 0xbe000000 if 32BIT
- default 0xffffffffbe000000 if 64BIT
-
-endif
diff --git a/board/imgtec/malta/MAINTAINERS b/board/imgtec/malta/MAINTAINERS
deleted file mode 100644
index b1cf297f4fac..000000000000
--- a/board/imgtec/malta/MAINTAINERS
+++ /dev/null
@@ -1,9 +0,0 @@
-MALTA BOARD
-M: Paul Burton <paul.burton@mips.com>
-S: Maintained
-F: board/imgtec/malta/
-F: include/configs/malta.h
-F: configs/malta64_defconfig
-F: configs/malta64el_defconfig
-F: configs/malta_defconfig
-F: configs/maltael_defconfig
diff --git a/board/imgtec/malta/Makefile b/board/imgtec/malta/Makefile
deleted file mode 100644
index d0d84010fc76..000000000000
--- a/board/imgtec/malta/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# (C) Copyright 2003-2006
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-
-obj-y = malta.o
-obj-y += lowlevel_init.o
-obj-y += superio.o
diff --git a/board/imgtec/malta/flash-malta-boot.tcl b/board/imgtec/malta/flash-malta-boot.tcl
deleted file mode 100644
index 972002a8e911..000000000000
--- a/board/imgtec/malta/flash-malta-boot.tcl
+++ /dev/null
@@ -1,38 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright (C) 2013 Imagination Technologies
-#
-# Programs a MIPS Malta boot flash with a flat binary image.
-
-proc flash-boot { binfile } {
- puts "flash monitor binary $binfile"
- config Coherent on
- config CoherencyDuringLoad on
-
- if {[endian]=="big"} {
- puts "CPU in BE mode"
- flash device sharp_16x32_be;
- } else {
- puts "CPU in LE mode"
- flash device sharp_16x32;
- }
-
- flash clear all;
- flash set 0xBE000000..0xBE0FFFFF
- flash erase sector 0xbe000000;
- flash erase sector 0xbe020000;
- flash erase sector 0xbe040000;
- flash erase sector 0xbe060000;
- flash erase sector 0xbe080000;
- flash erase sector 0xbe0a0000;
- flash erase sector 0xbe0c0000;
- flash erase sector 0xbe0e0000;
- puts "finished erasing boot flash";
-
- puts "programming flash, please be patient"
- load bin 0xbe000000 $binfile size4
-
- flash clear all
- config CoherencyDuringLoad off
- puts "finished programming boot flash";
-}
diff --git a/board/imgtec/malta/lowlevel_init.S b/board/imgtec/malta/lowlevel_init.S
deleted file mode 100644
index ecb4424fd92a..000000000000
--- a/board/imgtec/malta/lowlevel_init.S
+++ /dev/null
@@ -1,231 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (C) 2013 Gabor Juhos <juhosg@openwrt.org>
- */
-
-#include <config.h>
-#include <gt64120.h>
-#include <msc01.h>
-#include <pci.h>
-
-#include <asm/addrspace.h>
-#include <asm/asm.h>
-#include <asm/regdef.h>
-#include <asm/malta.h>
-#include <asm/mipsregs.h>
-
-#ifdef CONFIG_SYS_BIG_ENDIAN
-#define CPU_TO_GT32(_x) ((_x))
-#else
-#define CPU_TO_GT32(_x) ( \
- (((_x) & 0xff) << 24) | (((_x) & 0xff00) << 8) | \
- (((_x) & 0xff0000) >> 8) | (((_x) & 0xff000000) >> 24))
-#endif
-
- .text
- .set noreorder
-
- .globl lowlevel_init
-lowlevel_init:
- /* detect the core card */
- PTR_LI t0, CKSEG1ADDR(MALTA_REVISION)
- lw t0, 0(t0)
- srl t0, t0, MALTA_REVISION_CORID_SHF
- andi t0, t0, (MALTA_REVISION_CORID_MSK >> \
- MALTA_REVISION_CORID_SHF)
-
- /* core cards using the gt64120 system controller */
- li t1, MALTA_REVISION_CORID_CORE_LV
- beq t0, t1, _gt64120
-
- /* core cards using the MSC01 system controller */
- li t1, MALTA_REVISION_CORID_CORE_FPGA6
- beq t0, t1, _msc01
- nop
-
- /* unknown system controller */
- b .
- nop
-
- /*
- * Load BAR registers of GT64120 as done by YAMON
- *
- * based on a patch sent by Antony Pavlov <antonynpavlov@gmail.com>
- * to the barebox mailing list.
- * The subject of the original patch:
- * 'MIPS: qemu-malta: add YAMON-style GT64120 memory map'
- * URL:
- * http://www.mail-archive.com/barebox at lists.infradead.org/msg06128.html
- *
- * based on write_bootloader() in qemu.git/hw/mips_malta.c
- * see GT64120 manual and qemu.git/hw/gt64xxx.c for details
- */
-_gt64120:
- /* move GT64120 registers from 0x14000000 to 0x1be00000 */
- PTR_LI t1, CKSEG1ADDR(GT_DEF_BASE)
- li t0, CPU_TO_GT32(0xdf000000)
- sw t0, GT_ISD_OFS(t1)
-
- /* setup MEM-to-PCI0 mapping */
- PTR_LI t1, CKSEG1ADDR(MALTA_GT_BASE)
-
- /* setup PCI0 io window to 0x18000000-0x181fffff */
- li t0, CPU_TO_GT32(0xc0000000)
- sw t0, GT_PCI0IOLD_OFS(t1)
- li t0, CPU_TO_GT32(0x40000000)
- sw t0, GT_PCI0IOHD_OFS(t1)
-
- /* setup PCI0 mem windows */
- li t0, CPU_TO_GT32(0x80000000)
- sw t0, GT_PCI0M0LD_OFS(t1)
- li t0, CPU_TO_GT32(0x3f000000)
- sw t0, GT_PCI0M0HD_OFS(t1)
-
- li t0, CPU_TO_GT32(0xc1000000)
- sw t0, GT_PCI0M1LD_OFS(t1)
- li t0, CPU_TO_GT32(0x5e000000)
- sw t0, GT_PCI0M1HD_OFS(t1)
-
- jr ra
- nop
-
- /*
- *
- */
-_msc01:
- /* setup peripheral bus controller clock divide */
- PTR_LI t0, CKSEG1ADDR(MALTA_MSC01_PBC_BASE)
- li t1, 0x1 << MSC01_PBC_CLKCFG_SHF
- sw t1, MSC01_PBC_CLKCFG_OFS(t0)
-
- /* tweak peripheral bus controller timings */
- li t1, (0x1 << MSC01_PBC_CS0TIM_CDT_SHF) | \
- (0x1 << MSC01_PBC_CS0TIM_CAT_SHF)
- sw t1, MSC01_PBC_CS0TIM_OFS(t0)
- li t1, (0x0 << MSC01_PBC_CS0RW_RDT_SHF) | \
- (0x2 << MSC01_PBC_CS0RW_RAT_SHF) | \
- (0x0 << MSC01_PBC_CS0RW_WDT_SHF) | \
- (0x2 << MSC01_PBC_CS0RW_WAT_SHF)
- sw t1, MSC01_PBC_CS0RW_OFS(t0)
- lw t1, MSC01_PBC_CS0CFG_OFS(t0)
- li t2, MSC01_PBC_CS0CFG_DTYP_MSK
- and t1, t2
- ori t1, (0x0 << MSC01_PBC_CS0CFG_ADM_SHF) | \
- (0x3 << MSC01_PBC_CS0CFG_WSIDLE_SHF) | \
- (0x10 << MSC01_PBC_CS0CFG_WS_SHF)
- sw t1, MSC01_PBC_CS0CFG_OFS(t0)
-
- /* setup basic address decode */
- PTR_LI t0, CKSEG1ADDR(MALTA_MSC01_BIU_BASE)
- li t1, 0x0
- li t2, -CONFIG_SYS_MEM_SIZE
- sw t1, MSC01_BIU_MCBAS1L_OFS(t0)
- sw t2, MSC01_BIU_MCMSK1L_OFS(t0)
- sw t1, MSC01_BIU_MCBAS2L_OFS(t0)
- sw t2, MSC01_BIU_MCMSK2L_OFS(t0)
-
- /* initialise IP1 - unused */
- li t1, MALTA_MSC01_IP1_BASE
- li t2, -MALTA_MSC01_IP1_SIZE
- sw t1, MSC01_BIU_IP1BAS1L_OFS(t0)
- sw t2, MSC01_BIU_IP1MSK1L_OFS(t0)
- sw t1, MSC01_BIU_IP1BAS2L_OFS(t0)
- sw t2, MSC01_BIU_IP1MSK2L_OFS(t0)
-
- /* initialise IP2 - PCI */
- li t1, MALTA_MSC01_IP2_BASE1
- li t2, -MALTA_MSC01_IP2_SIZE1
- sw t1, MSC01_BIU_IP2BAS1L_OFS(t0)
- sw t2, MSC01_BIU_IP2MSK1L_OFS(t0)
- li t1, MALTA_MSC01_IP2_BASE2
- li t2, -MALTA_MSC01_IP2_SIZE2
- sw t1, MSC01_BIU_IP2BAS2L_OFS(t0)
- sw t2, MSC01_BIU_IP2MSK2L_OFS(t0)
-
- /* initialise IP3 - peripheral bus controller */
- li t1, MALTA_MSC01_IP3_BASE
- li t2, -MALTA_MSC01_IP3_SIZE
- sw t1, MSC01_BIU_IP3BAS1L_OFS(t0)
- sw t2, MSC01_BIU_IP3MSK1L_OFS(t0)
- sw t1, MSC01_BIU_IP3BAS2L_OFS(t0)
- sw t2, MSC01_BIU_IP3MSK2L_OFS(t0)
-
- /* setup PCI memory */
- PTR_LI t0, CKSEG1ADDR(MALTA_MSC01_PCI_BASE)
- li t1, MALTA_MSC01_PCIMEM_BASE
- li t2, (-MALTA_MSC01_PCIMEM_SIZE) & MSC01_PCI_SC2PMMSKL_MSK_MSK
- li t3, MALTA_MSC01_PCIMEM_MAP
- sw t1, MSC01_PCI_SC2PMBASL_OFS(t0)
- sw t2, MSC01_PCI_SC2PMMSKL_OFS(t0)
- sw t3, MSC01_PCI_SC2PMMAPL_OFS(t0)
-
- /* setup PCI I/O */
- li t1, MALTA_MSC01_PCIIO_BASE
- li t2, (-MALTA_MSC01_PCIIO_SIZE) & MSC01_PCI_SC2PIOMSKL_MSK_MSK
- li t3, MALTA_MSC01_PCIIO_MAP
- sw t1, MSC01_PCI_SC2PIOBASL_OFS(t0)
- sw t2, MSC01_PCI_SC2PIOMSKL_OFS(t0)
- sw t3, MSC01_PCI_SC2PIOMAPL_OFS(t0)
-
- /* setup PCI_BAR0 memory window */
- li t1, -CONFIG_SYS_MEM_SIZE
- sw t1, MSC01_PCI_BAR0_OFS(t0)
-
- /* setup PCI to SysCon/CPU translation */
- sw t1, MSC01_PCI_P2SCMSKL_OFS(t0)
- sw zero, MSC01_PCI_P2SCMAPL_OFS(t0)
-
- /* setup PCI vendor & device IDs */
- li t1, (PCI_VENDOR_ID_MIPS << MSC01_PCI_HEAD0_VENDORID_SHF) | \
- (PCI_DEVICE_ID_MIPS_MSC01 << MSC01_PCI_HEAD0_DEVICEID_SHF)
- sw t1, MSC01_PCI_HEAD0_OFS(t0)
-
- /* setup PCI subsystem vendor & device IDs */
- sw t1, MSC01_PCI_HEAD11_OFS(t0)
-
- /* setup PCI class, revision */
- li t1, (PCI_CLASS_BRIDGE_HOST << MSC01_PCI_HEAD2_CLASS_SHF) | \
- (0x1 << MSC01_PCI_HEAD2_REV_SHF)
- sw t1, MSC01_PCI_HEAD2_OFS(t0)
-
- /* ensure a sane setup */
- sw zero, MSC01_PCI_HEAD3_OFS(t0)
- sw zero, MSC01_PCI_HEAD4_OFS(t0)
- sw zero, MSC01_PCI_HEAD5_OFS(t0)
- sw zero, MSC01_PCI_HEAD6_OFS(t0)
- sw zero, MSC01_PCI_HEAD7_OFS(t0)
- sw zero, MSC01_PCI_HEAD8_OFS(t0)
- sw zero, MSC01_PCI_HEAD9_OFS(t0)
- sw zero, MSC01_PCI_HEAD10_OFS(t0)
- sw zero, MSC01_PCI_HEAD12_OFS(t0)
- sw zero, MSC01_PCI_HEAD13_OFS(t0)
- sw zero, MSC01_PCI_HEAD14_OFS(t0)
- sw zero, MSC01_PCI_HEAD15_OFS(t0)
-
- /* setup PCI command register */
- li t1, (PCI_COMMAND_FAST_BACK | \
- PCI_COMMAND_SERR | \
- PCI_COMMAND_PARITY | \
- PCI_COMMAND_MASTER | \
- PCI_COMMAND_MEMORY)
- sw t1, MSC01_PCI_HEAD1_OFS(t0)
-
- /* setup PCI byte swapping */
-#ifdef CONFIG_SYS_BIG_ENDIAN
- li t1, (0x1 << MSC01_PCI_SWAP_BAR0_BSWAP_SHF) | \
- (0x1 << MSC01_PCI_SWAP_IO_BSWAP_SHF)
- sw t1, MSC01_PCI_SWAP_OFS(t0)
-#else
- sw zero, MSC01_PCI_SWAP_OFS(t0)
-#endif
-
- /* enable PCI host configuration cycles */
- lw t1, MSC01_PCI_CFG_OFS(t0)
- li t2, MSC01_PCI_CFG_RA_MSK | \
- MSC01_PCI_CFG_G_MSK | \
- MSC01_PCI_CFG_EN_MSK
- or t1, t1, t2
- sw t1, MSC01_PCI_CFG_OFS(t0)
-
- jr ra
- nop
diff --git a/board/imgtec/malta/malta.c b/board/imgtec/malta/malta.c
deleted file mode 100644
index c04f727961de..000000000000
--- a/board/imgtec/malta/malta.c
+++ /dev/null
@@ -1,233 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (C) 2013 Gabor Juhos <juhosg@openwrt.org>
- * Copyright (C) 2013 Imagination Technologies
- */
-
-#include <common.h>
-#include <ide.h>
-#include <init.h>
-#include <net.h>
-#include <netdev.h>
-#include <pci.h>
-#include <pci_gt64120.h>
-#include <pci_msc01.h>
-#include <rtc.h>
-#include <asm/global_data.h>
-#include <linux/delay.h>
-
-#include <asm/addrspace.h>
-#include <asm/io.h>
-#include <asm/malta.h>
-
-#include "superio.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-enum core_card {
- CORE_UNKNOWN,
- CORE_LV,
- CORE_FPGA6,
-};
-
-enum sys_con {
- SYSCON_UNKNOWN,
- SYSCON_GT64120,
- SYSCON_MSC01,
-};
-
-static void malta_lcd_puts(const char *str)
-{
- int i;
- void *reg = (void *)CKSEG1ADDR(MALTA_ASCIIPOS0);
-
- /* print up to 8 characters of the string */
- for (i = 0; i < min((int)strlen(str), 8); i++) {
- __raw_writel(str[i], reg);
- reg += MALTA_ASCIIPOS1 - MALTA_ASCIIPOS0;
- }
-
- /* fill the rest of the display with spaces */
- for (; i < 8; i++) {
- __raw_writel(' ', reg);
- reg += MALTA_ASCIIPOS1 - MALTA_ASCIIPOS0;
- }
-}
-
-static enum core_card malta_core_card(void)
-{
- u32 corid, rev;
- const void *reg = (const void *)CKSEG1ADDR(MALTA_REVISION);
-
- rev = __raw_readl(reg);
- corid = (rev & MALTA_REVISION_CORID_MSK) >> MALTA_REVISION_CORID_SHF;
-
- switch (corid) {
- case MALTA_REVISION_CORID_CORE_LV:
- return CORE_LV;
-
- case MALTA_REVISION_CORID_CORE_FPGA6:
- return CORE_FPGA6;
-
- default:
- return CORE_UNKNOWN;
- }
-}
-
-static enum sys_con malta_sys_con(void)
-{
- switch (malta_core_card()) {
- case CORE_LV:
- return SYSCON_GT64120;
-
- case CORE_FPGA6:
- return SYSCON_MSC01;
-
- default:
- return SYSCON_UNKNOWN;
- }
-}
-
-int dram_init(void)
-{
- gd->ram_size = CONFIG_SYS_MEM_SIZE;
-
- return 0;
-}
-
-int checkboard(void)
-{
- enum core_card core;
-
- malta_lcd_puts("U-Boot");
- puts("Board: MIPS Malta");
-
- core = malta_core_card();
- switch (core) {
- case CORE_LV:
- puts(" CoreLV");
- break;
-
- case CORE_FPGA6:
- puts(" CoreFPGA6");
- break;
-
- default:
- puts(" CoreUnknown");
- }
-
- putc('\n');
- return 0;
-}
-
-int board_eth_init(struct bd_info *bis)
-{
- return pci_eth_init(bis);
-}
-
-void _machine_restart(void)
-{
- void __iomem *reset_base;
-
- reset_base = (void __iomem *)CKSEG1ADDR(MALTA_RESET_BASE);
- __raw_writel(GORESET, reset_base);
- mdelay(1000);
-}
-
-int board_early_init_f(void)
-{
- ulong io_base;
-
- /* choose correct PCI I/O base */
- switch (malta_sys_con()) {
- case SYSCON_GT64120:
- io_base = CKSEG1ADDR(MALTA_GT_PCIIO_BASE);
- break;
-
- case SYSCON_MSC01:
- io_base = CKSEG1ADDR(MALTA_MSC01_PCIIO_BASE);
- break;
-
- default:
- return -1;
- }
-
- set_io_port_base(io_base);
-
- /* setup FDC37M817 super I/O controller */
- malta_superio_init();
-
- return 0;
-}
-
-int misc_init_r(void)
-{
- rtc_reset();
-
- return 0;
-}
-
-void pci_init_board(void)
-{
- pci_dev_t bdf;
- u32 val32;
- u8 val8;
-
- switch (malta_sys_con()) {
- case SYSCON_GT64120:
- gt64120_pci_init((void *)CKSEG1ADDR(MALTA_GT_BASE),
- 0x00000000, 0x00000000, CONFIG_SYS_MEM_SIZE,
- 0x10000000, 0x10000000, 128 * 1024 * 1024,
- 0x00000000, 0x00000000, 0x20000);
- break;
-
- default:
- case SYSCON_MSC01:
- msc01_pci_init((void *)CKSEG1ADDR(MALTA_MSC01_PCI_BASE),
- 0x00000000, 0x00000000, CONFIG_SYS_MEM_SIZE,
- MALTA_MSC01_PCIMEM_MAP,
- CKSEG1ADDR(MALTA_MSC01_PCIMEM_BASE),
- MALTA_MSC01_PCIMEM_SIZE, MALTA_MSC01_PCIIO_MAP,
- 0x00000000, MALTA_MSC01_PCIIO_SIZE);
- break;
- }
-
- bdf = pci_find_device(PCI_VENDOR_ID_INTEL,
- PCI_DEVICE_ID_INTEL_82371AB_0, 0);
- if (bdf == -1)
- panic("Failed to find PIIX4 PCI bridge\n");
-
- /* setup PCI interrupt routing */
- pci_write_config_byte(bdf, PCI_CFG_PIIX4_PIRQRCA, 10);
- pci_write_config_byte(bdf, PCI_CFG_PIIX4_PIRQRCB, 10);
- pci_write_config_byte(bdf, PCI_CFG_PIIX4_PIRQRCC, 11);
- pci_write_config_byte(bdf, PCI_CFG_PIIX4_PIRQRCD, 11);
-
- /* mux SERIRQ onto SERIRQ pin */
- pci_read_config_dword(bdf, PCI_CFG_PIIX4_GENCFG, &val32);
- val32 |= PCI_CFG_PIIX4_GENCFG_SERIRQ;
- pci_write_config_dword(bdf, PCI_CFG_PIIX4_GENCFG, val32);
-
- /* enable SERIRQ - Linux currently depends upon this */
- pci_read_config_byte(bdf, PCI_CFG_PIIX4_SERIRQC, &val8);
- val8 |= PCI_CFG_PIIX4_SERIRQC_EN | PCI_CFG_PIIX4_SERIRQC_CONT;
- pci_write_config_byte(bdf, PCI_CFG_PIIX4_SERIRQC, val8);
-
- bdf = pci_find_device(PCI_VENDOR_ID_INTEL,
- PCI_DEVICE_ID_INTEL_82371AB, 0);
- if (bdf == -1)
- panic("Failed to find PIIX4 IDE controller\n");
-
- /* enable bus master & IO access */
- val32 |= PCI_COMMAND_MASTER | PCI_COMMAND_IO;
- pci_write_config_dword(bdf, PCI_COMMAND, val32);
-
- /* set latency */
- pci_write_config_byte(bdf, PCI_LATENCY_TIMER, 0x40);
-
- /* enable IDE/ATA */
- pci_write_config_dword(bdf, PCI_CFG_PIIX4_IDETIM_PRI,
- PCI_CFG_PIIX4_IDETIM_IDE);
- pci_write_config_dword(bdf, PCI_CFG_PIIX4_IDETIM_SEC,
- PCI_CFG_PIIX4_IDETIM_IDE);
-}
diff --git a/board/imgtec/malta/superio.c b/board/imgtec/malta/superio.c
deleted file mode 100644
index aba11e25be31..000000000000
--- a/board/imgtec/malta/superio.c
+++ /dev/null
@@ -1,62 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2013 Imagination Technologies
- * Author: Paul Burton <paul.burton@mips.com>
- *
- * Setup code for the FDC37M817 super I/O controller
- */
-
-#include <common.h>
-#include <asm/io.h>
-
-#define SIO_CONF_PORT 0x3f0
-#define SIO_DATA_PORT 0x3f1
-
-enum sio_conf_key {
- SIOCONF_DEVNUM = 0x07,
- SIOCONF_ACTIVATE = 0x30,
- SIOCONF_ENTER_SETUP = 0x55,
- SIOCONF_BASE_HIGH = 0x60,
- SIOCONF_BASE_LOW = 0x61,
- SIOCONF_PRIMARY_INT = 0x70,
- SIOCONF_EXIT_SETUP = 0xaa,
- SIOCONF_MODE = 0xf0,
-};
-
-static struct {
- u8 key;
- u8 data;
-} sio_config[] = {
- /* tty0 */
- { SIOCONF_DEVNUM, 0x04 },
- { SIOCONF_BASE_HIGH, 0x03 },
- { SIOCONF_BASE_LOW, 0xf8 },
- { SIOCONF_MODE, 0x02 },
- { SIOCONF_PRIMARY_INT, 0x04 },
- { SIOCONF_ACTIVATE, 0x01 },
-
- /* tty1 */
- { SIOCONF_DEVNUM, 0x05 },
- { SIOCONF_BASE_HIGH, 0x02 },
- { SIOCONF_BASE_LOW, 0xf8 },
- { SIOCONF_MODE, 0x02 },
- { SIOCONF_PRIMARY_INT, 0x03 },
- { SIOCONF_ACTIVATE, 0x01 },
-};
-
-void malta_superio_init(void)
-{
- unsigned i;
-
- /* enter config state */
- outb(SIOCONF_ENTER_SETUP, SIO_CONF_PORT);
-
- /* configure peripherals */
- for (i = 0; i < ARRAY_SIZE(sio_config); i++) {
- outb(sio_config[i].key, SIO_CONF_PORT);
- outb(sio_config[i].data, SIO_DATA_PORT);
- }
-
- /* exit config state */
- outb(SIOCONF_EXIT_SETUP, SIO_CONF_PORT);
-}
diff --git a/board/imgtec/malta/superio.h b/board/imgtec/malta/superio.h
deleted file mode 100644
index 11e9cef978e8..000000000000
--- a/board/imgtec/malta/superio.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2013 Imagination Technologies
- * Author: Paul Burton <paul.burton@mips.com>
- *
- * Setup code for the FDC37M817 super I/O controller
- */
-
-#ifndef __BOARD_MALTA_SUPERIO_H__
-#define __BOARD_MALTA_SUPERIO_H__
-
-void malta_superio_init(void);
-
-#endif /* __BOARD_MALTA_SUPERIO_H__ */
diff --git a/configs/malta64_defconfig b/configs/malta64_defconfig
deleted file mode 100644
index 878dc6ee05bc..000000000000
--- a/configs/malta64_defconfig
+++ /dev/null
@@ -1,33 +0,0 @@
-CONFIG_MIPS=y
-CONFIG_SYS_TEXT_BASE=0xFFFFFFFFBE000000
-CONFIG_ENV_SIZE=0x20000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_TARGET_MALTA=y
-CONFIG_DEFAULT_DEVICE_TREE="mti,malta"
-CONFIG_CPU_MIPS64_R2=y
-# CONFIG_AUTOBOOT is not set
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_MISC_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_SYS_PROMPT="malta # "
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_IDE=y
-# CONFIG_CMD_LOADB is not set
-# CONFIG_CMD_LOADS is not set
-CONFIG_CMD_PCI=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-# CONFIG_CMD_NFS is not set
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-# CONFIG_ISO_PARTITION is not set
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0xFFFFFFFFBE3E0000
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_PCNET=y
-CONFIG_PCI=y
-CONFIG_RTC_MC146818=y
-CONFIG_SYS_NS16550=y
diff --git a/configs/malta64el_defconfig b/configs/malta64el_defconfig
deleted file mode 100644
index 7dfe67355ff8..000000000000
--- a/configs/malta64el_defconfig
+++ /dev/null
@@ -1,35 +0,0 @@
-CONFIG_MIPS=y
-CONFIG_SYS_TEXT_BASE=0xFFFFFFFFBE000000
-CONFIG_ENV_SIZE=0x20000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_TARGET_MALTA=y
-CONFIG_BUILD_TARGET="u-boot-swap.bin"
-CONFIG_DEFAULT_DEVICE_TREE="mti,malta"
-CONFIG_SYS_LITTLE_ENDIAN=y
-CONFIG_CPU_MIPS64_R2=y
-# CONFIG_AUTOBOOT is not set
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_MISC_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_SYS_PROMPT="maltael # "
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_IDE=y
-# CONFIG_CMD_LOADB is not set
-# CONFIG_CMD_LOADS is not set
-CONFIG_CMD_PCI=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-# CONFIG_CMD_NFS is not set
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-# CONFIG_ISO_PARTITION is not set
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0xFFFFFFFFBE3E0000
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_PCNET=y
-CONFIG_PCI=y
-CONFIG_RTC_MC146818=y
-CONFIG_SYS_NS16550=y
diff --git a/configs/malta_defconfig b/configs/malta_defconfig
deleted file mode 100644
index 304f2198baaf..000000000000
--- a/configs/malta_defconfig
+++ /dev/null
@@ -1,32 +0,0 @@
-CONFIG_MIPS=y
-CONFIG_SYS_TEXT_BASE=0xBE000000
-CONFIG_ENV_SIZE=0x20000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_TARGET_MALTA=y
-CONFIG_DEFAULT_DEVICE_TREE="mti,malta"
-# CONFIG_AUTOBOOT is not set
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_MISC_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_SYS_PROMPT="malta # "
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_IDE=y
-# CONFIG_CMD_LOADB is not set
-# CONFIG_CMD_LOADS is not set
-CONFIG_CMD_PCI=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-# CONFIG_CMD_NFS is not set
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-# CONFIG_ISO_PARTITION is not set
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0xBE3E0000
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_PCNET=y
-CONFIG_PCI=y
-CONFIG_RTC_MC146818=y
-CONFIG_SYS_NS16550=y
diff --git a/configs/maltael_defconfig b/configs/maltael_defconfig
deleted file mode 100644
index 7436e4e94390..000000000000
--- a/configs/maltael_defconfig
+++ /dev/null
@@ -1,34 +0,0 @@
-CONFIG_MIPS=y
-CONFIG_SYS_TEXT_BASE=0xBE000000
-CONFIG_ENV_SIZE=0x20000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_TARGET_MALTA=y
-CONFIG_BUILD_TARGET="u-boot-swap.bin"
-CONFIG_DEFAULT_DEVICE_TREE="mti,malta"
-CONFIG_SYS_LITTLE_ENDIAN=y
-# CONFIG_AUTOBOOT is not set
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_MISC_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_SYS_PROMPT="maltael # "
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_IDE=y
-# CONFIG_CMD_LOADB is not set
-# CONFIG_CMD_LOADS is not set
-CONFIG_CMD_PCI=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-# CONFIG_CMD_NFS is not set
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-# CONFIG_ISO_PARTITION is not set
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0xBE3E0000
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_PCNET=y
-CONFIG_PCI=y
-CONFIG_RTC_MC146818=y
-CONFIG_SYS_NS16550=y
diff --git a/include/configs/malta.h b/include/configs/malta.h
deleted file mode 100644
index 9602773ff91f..000000000000
--- a/include/configs/malta.h
+++ /dev/null
@@ -1,81 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (C) 2013 Gabor Juhos <juhosg@openwrt.org>
- */
-
-#ifndef _MALTA_CONFIG_H
-#define _MALTA_CONFIG_H
-
-/*
- * System configuration
- */
-#define CONFIG_MALTA
-
-#define CONFIG_MEMSIZE_IN_BYTES
-
-#define CONFIG_PCI_GT64120
-#define CONFIG_PCI_MSC01
-
-#define CONFIG_SYS_ISA_IO_BASE_ADDRESS 0
-
-/*
- * CPU Configuration
- */
-#define CONFIG_SYS_MHZ 250 /* arbitrary value */
-#define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 1000000)
-
-/*
- * Memory map
- */
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-
-#ifdef CONFIG_64BIT
-# define CONFIG_SYS_SDRAM_BASE 0xffffffff80000000
-#else
-# define CONFIG_SYS_SDRAM_BASE 0x80000000
-#endif
-#define CONFIG_SYS_MEM_SIZE (256 * 1024 * 1024)
-
-#define CONFIG_SYS_INIT_SP_OFFSET 0x400000
-
-#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x01000000)
-
-#define CONFIG_SYS_MALLOC_LEN (128 * 1024)
-#define CONFIG_SYS_BOOTPARAMS_LEN (128 * 1024)
-#define CONFIG_SYS_BOOTM_LEN (64 * 1024 * 1024)
-
-/*
- * Serial driver
- */
-#define CONFIG_SYS_NS16550_PORT_MAPPED
-
-/*
- * Flash configuration
- */
-#ifdef CONFIG_64BIT
-# define CONFIG_SYS_FLASH_BASE 0xffffffffbe000000
-#else
-# define CONFIG_SYS_FLASH_BASE 0xbe000000
-#endif
-#define CONFIG_SYS_MAX_FLASH_BANKS 1
-#define CONFIG_SYS_MAX_FLASH_SECT 128
-
-/*
- * Environment
- */
-
-/*
- * IDE/ATA
- */
-#define CONFIG_SYS_IDE_MAXBUS 1
-#define CONFIG_SYS_IDE_MAXDEVICE 2
-#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_ISA_IO_BASE_ADDRESS
-#define CONFIG_SYS_ATA_IDE0_OFFSET 0x01f0
-#define CONFIG_SYS_ATA_DATA_OFFSET 0
-#define CONFIG_SYS_ATA_REG_OFFSET 0
-
-/*
- * Commands
- */
-
-#endif /* _MALTA_CONFIG_H */
--
2.17.1