[PATCH 07/27] ppc: Remove sbc8349 board

Paul Gortmaker
2021-05-15T19:16:40Z

[[PATCH 07/27] ppc: Remove sbc8349 board] On 14/05/2021 (Fri 21:34) Tom Rini wrote:

> This board has not been converted to CONFIG_DM_MMC by the deadline.
> Remove it.
>
> Cc: Paul Gortmaker <paul.gortmaker@windriver.com>

Ack - this was removed in the linux-kernel already.

Thanks,
Paul.
--

> Signed-off-by: Tom Rini <trini@konsulko.com>
> ---
> arch/powerpc/cpu/mpc83xx/Kconfig | 5 -
> board/sbc8349/Kconfig | 9 -
> board/sbc8349/MAINTAINERS | 8 -
> board/sbc8349/Makefile | 6 -
> board/sbc8349/README | 127 ------------
> board/sbc8349/pci.c | 70 -------
> board/sbc8349/sbc8349.c | 243 -----------------------
> configs/sbc8349_PCI_33_defconfig | 123 ------------
> configs/sbc8349_PCI_66_defconfig | 123 ------------
> configs/sbc8349_defconfig | 101 ----------
> include/configs/sbc8349.h | 322 -------------------------------
> 11 files changed, 1137 deletions(-)
> delete mode 100644 board/sbc8349/Kconfig
> delete mode 100644 board/sbc8349/MAINTAINERS
> delete mode 100644 board/sbc8349/Makefile
> delete mode 100644 board/sbc8349/README
> delete mode 100644 board/sbc8349/pci.c
> delete mode 100644 board/sbc8349/sbc8349.c
> delete mode 100644 configs/sbc8349_PCI_33_defconfig
> delete mode 100644 configs/sbc8349_PCI_66_defconfig
> delete mode 100644 configs/sbc8349_defconfig
> delete mode 100644 include/configs/sbc8349.h
>
> diff --git a/arch/powerpc/cpu/mpc83xx/Kconfig b/arch/powerpc/cpu/mpc83xx/Kconfig
> index ff85834c460c..e0bdfc4b9716 100644
> --- a/arch/powerpc/cpu/mpc83xx/Kconfig
> +++ b/arch/powerpc/cpu/mpc83xx/Kconfig
> @@ -12,10 +12,6 @@ config TARGET_MPC8308_P1M
> bool "Support mpc8308_p1m"
> select ARCH_MPC8308
>
> -config TARGET_SBC8349
> - bool "Support sbc8349"
> - select ARCH_MPC8349
> -
> config TARGET_VE8313
> bool "Support ve8313"
> select ARCH_MPC8313
> @@ -312,7 +308,6 @@ source "board/freescale/mpc837xerdb/Kconfig"
> source "board/ids/ids8313/Kconfig"
> source "board/keymile/Kconfig"
> source "board/mpc8308_p1m/Kconfig"
> -source "board/sbc8349/Kconfig"
> source "board/tqc/tqm834x/Kconfig"
> source "board/ve8313/Kconfig"
> source "board/gdsys/mpc8308/Kconfig"
> diff --git a/board/sbc8349/Kconfig b/board/sbc8349/Kconfig
> deleted file mode 100644
> index 129d6b92ec57..000000000000
> --- a/board/sbc8349/Kconfig
> +++ /dev/null
> @@ -1,9 +0,0 @@
> -if TARGET_SBC8349
> -
> -config SYS_BOARD
> - default "sbc8349"
> -
> -config SYS_CONFIG_NAME
> - default "sbc8349"
> -
> -endif
> diff --git a/board/sbc8349/MAINTAINERS b/board/sbc8349/MAINTAINERS
> deleted file mode 100644
> index af95c1dd0d23..000000000000
> --- a/board/sbc8349/MAINTAINERS
> +++ /dev/null
> @@ -1,8 +0,0 @@
> -SBC8349 BOARD
> -M: Paul Gortmaker <paul.gortmaker@windriver.com>
> -S: Maintained
> -F: board/sbc8349/
> -F: include/configs/sbc8349.h
> -F: configs/sbc8349_defconfig
> -F: configs/sbc8349_PCI_33_defconfig
> -F: configs/sbc8349_PCI_66_defconfig
> diff --git a/board/sbc8349/Makefile b/board/sbc8349/Makefile
> deleted file mode 100644
> index c469174085d9..000000000000
> --- a/board/sbc8349/Makefile
> +++ /dev/null
> @@ -1,6 +0,0 @@
> -# SPDX-License-Identifier: GPL-2.0+
> -#
> -# Copyright (c) 2006 Wind River Systems, Inc.
> -
> -obj-y += sbc8349.o
> -obj-$(CONFIG_PCI) += pci.o
> diff --git a/board/sbc8349/README b/board/sbc8349/README
> deleted file mode 100644
> index 3c142e040762..000000000000
> --- a/board/sbc8349/README
> +++ /dev/null
> @@ -1,127 +0,0 @@
> -
> -
> - U-Boot for Wind River SBC834x Boards
> - ====================================
> -
> -
> -The Wind River SBC834x board is a 6U form factor (not CPCI) reference
> -design that uses the MPC8347E or MPC8349E processor. U-Boot support
> -for this board is heavily based on the existing U-Boot support for
> -Freescale MPC8349 reference boards.
> -
> -Support has been primarily tested on the SBC8349 version of the board,
> -although earlier versions were also tested on the SBC8347. The primary
> -difference in the two is the level of PCI functionality.
> -
> - http://www.windriver.com/products/OCD/SBC8347E_49E/
> -
> -
> -Flash Details:
> -==============
> -
> -The flash type is intel 28F640Jx (4096x16) [one device]. Base address
> -is 0xFF80_0000 which is also where the Hardware Reset Configuration
> -Word (HRCW) is stored. Caution should be used to not reset the
> -board without having a valid HRCW in place (i.e. erased flash) as
> -then a Wind River ICE will be required to restore the HRCW and flash
> -image.
> -
> -
> -Restoring a corrupted or missing flash image:
> -=============================================
> -
> -Note that U-Boot versions up to and including 2009.06 had essentially
> -two copies of U-Boot in flash; one at the very beginning, which set
> -the HRCW, and one at the very end, which was the image that was run.
> -As of this point in time, the two have been combined into just one
> -at the beginning of flash, which provides both the HRCW, and the image
> -that is executed. This frees up the remainder of flash for other uses.
> -Use of the U-Boot command "fli" will indicate what parts are in use.
> -Details for storing U-Boot to flash using a Wind River ICE can be found
> -on page 19 of the board manual (request ERG-00328-001). The following
> -is a summary of that information:
> -
> - - Connect ICE and establish connection to it from WorkBench/OCD.
> - - Ensure you have background mode (BKM) in the OCD terminal window.
> - - Select the appropriate flash type (listed above)
> - - Prepare a U-Boot image by using the Wind River Convert utility;
> - by using "Convert and Add file" on the ELF file from your build.
> - Convert from FF80_0000 to FFFF_FFFF (or to FF83_FFFF if you are
> - trying to preserve your old environment settings and user flash).
> - - Set the start address of the erase/flash process to FF80_0000
> - - Set the target RAM required to 64kB.
> - - Select sectors for erasing (see note on environment below)
> - - Select Erase and Reprogram.
> -
> -Note that some versions of the register files used with Workbench
> -would zero some TSEC registers, which inhibits ethernet operation
> -by U-Boot when this register file is played to the target. Using
> -"INN" in the OCD terminal window instead of "IN" before the "GO"
> -will not play the register file, and allow U-Boot to use the TSEC
> -interface while executed from the ICE "GO" command.
> -
> -Alternatively, you can locate the register file which will be named
> -WRS_SBC8349_PCT00328001.reg or similar) and "REM" out all the lines
> -beginning with "SCGA TSEC1" and "SCGA TSEC2". This allows you to
> -use all the remaining register file content.
> -
> -If you wish to preserve your prior U-Boot environment settings,
> -then convert (and erase to) 0xFF83FFFF instead of 0xFFFFFFFF.
> -The size for converting (and erasing) must be at least as large
> -as u-boot.bin.
> -
> -
> -Updating U-Boot with U-Boot:
> -============================
> -
> -This procedure is very similar to other boards that have U-Boot installed.
> -Assuming that the network has been configured, and that the new u-boot.bin
> -has been copied to the TFTP server, the commands are:
> -
> - tftp 200000 u-boot.bin
> - protect off all
> - erase ff800000 ff83ffff
> - cp.b 200000 ff800000 40000
> - protect on all
> -
> -You may wish to do a "md ff800000 20" operation as a prefix and postfix
> -to the above steps to inspect/compare the HRCW before/after as an extra
> -safety check before resetting the board upon completion of the reflash.
> -
> -PCI:
> -====
> -
> -There are three configuration choices:
> - sbc8349_config
> - sbc8349_PCI_33_config
> - sbc8349_PCI_66_config
> -
> -The 1st does not enable CONFIG_PCI, and assumes that the PCI slot
> -will be left empty (M66EN high), and so the board will operate with
> -a base clock of 66MHz. Note that you need both PCI enabled in U-Boot
> -and linux in order to have functional PCI under linux. The only
> -reason for choosing to not enable PCI would be if you had a very
> -early (rev 1.0) CPU with possible PCI issues.
> -
> -The second enables PCI support and builds for a 33MHz clock rate. Note
> -that if a 33MHz 32bit card is inserted in the slot, then the whole board
> -will clock down to a 33MHz base clock instead of the default 66MHz. This
> -will change the baud clocks and mess up your serial console output if you
> -were previously running at 66MHz. If you want to use a 33MHz PCI card,
> -then you should build a U-Boot with sbc8349_PCI_33_config and store this
> -to flash prior to powering down the board and inserting the 33MHz PCI
> -card.
> -
> -The third option builds PCI support in, and leaves the clocking at the
> -default 66MHz. This has been tested with an intel PCI-X e1000 card.
> -This is also the appropriate choice for people with a recent (non 1.0)
> -CPU who currently have the PCI slot physically empty, but intend to
> -possibly add a PCI-X card at a later date.
> -
> - => pci
> - Scanning PCI devices on bus 0
> - BusDevFun VendorId DeviceId Device Class Sub-Class
> - _____________________________________________________________
> - 00.00.00 0x1957 0x0080 Processor 0x20
> - 00.11.00 0x8086 0x1026 Network controller 0x00
> - =>
> diff --git a/board/sbc8349/pci.c b/board/sbc8349/pci.c
> deleted file mode 100644
> index 26c4f24e4f8b..000000000000
> --- a/board/sbc8349/pci.c
> +++ /dev/null
> @@ -1,70 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0+
> -/*
> - * pci.c -- WindRiver SBC8349 PCI board support.
> - * Copyright (c) 2006 Wind River Systems, Inc.
> - * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
> - *
> - * Based on MPC8349 PCI support but w/o PIB related code.
> - */
> -
> -#include <init.h>
> -#include <asm/mmu.h>
> -#include <asm/io.h>
> -#include <common.h>
> -#include <mpc83xx.h>
> -#include <pci.h>
> -#include <i2c.h>
> -#include <asm/fsl_i2c.h>
> -#include <linux/delay.h>
> -
> -static struct pci_region pci1_regions[] = {
> - {
> - bus_start: CONFIG_SYS_PCI1_MEM_BASE,
> - phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
> - size: CONFIG_SYS_PCI1_MEM_SIZE,
> - flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
> - },
> - {
> - bus_start: CONFIG_SYS_PCI1_IO_BASE,
> - phys_start: CONFIG_SYS_PCI1_IO_PHYS,
> - size: CONFIG_SYS_PCI1_IO_SIZE,
> - flags: PCI_REGION_IO
> - },
> - {
> - bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
> - phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
> - size: CONFIG_SYS_PCI1_MMIO_SIZE,
> - flags: PCI_REGION_MEM
> - },
> -};
> -
> -/*
> - * pci_init_board()
> - *
> - * NOTICE: PCI2 is not supported. There is only one
> - * physical PCI slot on the board.
> - *
> - */
> -void
> -pci_init_board(void)
> -{
> - volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
> - volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
> - volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
> - struct pci_region *reg[] = { pci1_regions };
> -
> - /* Enable all 8 PCI_CLK_OUTPUTS */
> - clk->occr = 0xff000000;
> - udelay(2000);
> -
> - /* Configure PCI Local Access Windows */
> - pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
> - pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G;
> -
> - pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
> - pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_4M;
> -
> - udelay(2000);
> -
> - mpc83xx_pci_init(1, reg);
> -}
> diff --git a/board/sbc8349/sbc8349.c b/board/sbc8349/sbc8349.c
> deleted file mode 100644
> index b440a0b17e97..000000000000
> --- a/board/sbc8349/sbc8349.c
> +++ /dev/null
> @@ -1,243 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0+
> -/*
> - * sbc8349.c -- WindRiver SBC8349 board support.
> - * Copyright (c) 2006-2007 Wind River Systems, Inc.
> - *
> - * Paul Gortmaker <paul.gortmaker@windriver.com>
> - * Based on board/mpc8349emds/mpc8349emds.c (and previous 834x releases.)
> - */
> -
> -#include <common.h>
> -#include <fdt_support.h>
> -#include <init.h>
> -#include <ioports.h>
> -#include <mpc83xx.h>
> -#include <asm/bitops.h>
> -#include <asm/global_data.h>
> -#include <asm/mpc8349_pci.h>
> -#include <i2c.h>
> -#include <spd_sdram.h>
> -#include <miiphy.h>
> -#if defined(CONFIG_OF_LIBFDT)
> -#include <linux/libfdt.h>
> -#endif
> -#include <linux/delay.h>
> -
> -DECLARE_GLOBAL_DATA_PTR;
> -
> -int fixed_sdram(void);
> -void sdram_init(void);
> -
> -#if defined(CONFIG_DDR_ECC) && defined(CONFIG_MPC83xx)
> -void ddr_enable_ecc(unsigned int dram_size);
> -#endif
> -
> -#ifdef CONFIG_BOARD_EARLY_INIT_F
> -int board_early_init_f (void)
> -{
> - return 0;
> -}
> -#endif
> -
> -#define ns2clk(ns) (ns / (1000000000 / CONFIG_8349_CLKIN) + 1)
> -
> -int dram_init(void)
> -{
> - volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
> - u32 msize = 0;
> -
> - if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
> - return -1;
> -
> - /* DDR SDRAM - Main SODIMM */
> - im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & LAWBAR_BAR;
> -#if defined(CONFIG_SPD_EEPROM)
> - msize = spd_sdram();
> -#else
> - msize = fixed_sdram();
> -#endif
> - /*
> - * Initialize SDRAM if it is on local bus.
> - */
> - sdram_init();
> -
> -#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
> - /*
> - * Initialize and enable DDR ECC.
> - */
> - ddr_enable_ecc(msize * 1024 * 1024);
> -#endif
> - /* set total bus SDRAM size(bytes) -- DDR */
> - gd->ram_size = msize * 1024 * 1024;
> -
> - return 0;
> -}
> -
> -#if !defined(CONFIG_SPD_EEPROM)
> -/*************************************************************************
> - * fixed sdram init -- doesn't use serial presence detect.
> - ************************************************************************/
> -int fixed_sdram(void)
> -{
> - volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
> - u32 msize = CONFIG_SYS_DDR_SIZE;
> - u32 ddr_size = msize << 20; /* DDR size in bytes */
> - u32 ddr_size_log2 = __ilog2(msize);
> -
> - im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000;
> - im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
> -
> -#if (CONFIG_SYS_DDR_SIZE != 256)
> -#warning Currently any ddr size other than 256 is not supported
> -#endif
> -
> -#if ((CONFIG_SYS_SDRAM_BASE & 0x00FFFFFF) != 0)
> -#warning Chip select bounds is only configurable in 16MB increments
> -#endif
> - im->ddr.csbnds[2].csbnds =
> - ((CONFIG_SYS_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
> - (((CONFIG_SYS_SDRAM_BASE + ddr_size - 1) >>
> - CSBNDS_EA_SHIFT) & CSBNDS_EA);
> - im->ddr.cs_config[2] = CONFIG_SYS_DDR_CS2_CONFIG;
> -
> - /* currently we use only one CS, so disable the other banks */
> - im->ddr.cs_config[0] = 0;
> - im->ddr.cs_config[1] = 0;
> - im->ddr.cs_config[3] = 0;
> -
> - im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
> - im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
> -
> - im->ddr.sdram_cfg =
> - SDRAM_CFG_SREN
> -#if defined(CONFIG_DDR_2T_TIMING)
> - | SDRAM_CFG_2T_EN
> -#endif
> - | SDRAM_CFG_SDRAM_TYPE_DDR1;
> -#if defined (CONFIG_DDR_32BIT)
> - /* for 32-bit mode burst length is 8 */
> - im->ddr.sdram_cfg |= (SDRAM_CFG_32_BE | SDRAM_CFG_8_BE);
> -#endif
> - im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
> -
> - im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
> - udelay(200);
> -
> - /* enable DDR controller */
> - im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
> - return msize;
> -}
> -#endif/*!CONFIG_SYS_SPD_EEPROM*/
> -
> -
> -int checkboard (void)
> -{
> - puts("Board: Wind River SBC834x\n");
> - return 0;
> -}
> -
> -/*
> - * if board is fitted with SDRAM
> - */
> -#if defined(CONFIG_SYS_BR2_PRELIM) \
> - && defined(CONFIG_SYS_OR2_PRELIM) \
> - && defined(CONFIG_SYS_LBLAWBAR2_PRELIM) \
> - && defined(CONFIG_SYS_LBLAWAR2_PRELIM)
> -/*
> - * Initialize SDRAM memory on the Local Bus.
> - */
> -
> -void sdram_init(void)
> -{
> - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
> - volatile fsl_lbc_t *lbc = &immap->im_lbc;
> - uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
> - const u32 lsdmr_common = LSDMR_RFEN | LSDMR_BSMA1516 | LSDMR_RFCR8 |
> - LSDMR_PRETOACT6 | LSDMR_ACTTORW3 | LSDMR_BL8 |
> - LSDMR_WRC3 | LSDMR_CL3;
> -
> - puts("\n SDRAM on Local Bus: ");
> - print_size (CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
> -
> - /*
> - * Setup SDRAM Base and Option Registers, already done in cpu_init.c
> - */
> -
> - /* setup mtrpt, lsrt and lbcr for LB bus */
> - lbc->lbcr = 0x00000000;
> - /* LB refresh timer prescal, 266MHz/32 */
> - lbc->mrtpr = 0x20000000;
> - /* LB sdram refresh timer, about 6us */
> - lbc->lsrt = 0x32000000;
> - asm("sync");
> -
> - /*
> - * Configure the SDRAM controller Machine Mode Register.
> - */
> - /* 0x40636733; normal operation */
> - lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL;
> -
> - /* 0x68636733; precharge all the banks */
> - lbc->lsdmr = lsdmr_common | LSDMR_OP_PCHALL;
> - asm("sync");
> - *sdram_addr = 0xff;
> - udelay(100);
> -
> - /* 0x48636733; auto refresh */
> - lbc->lsdmr = lsdmr_common | LSDMR_OP_ARFRSH;
> - asm("sync");
> - /*1 times*/
> - *sdram_addr = 0xff;
> - udelay(100);
> - /*2 times*/
> - *sdram_addr = 0xff;
> - udelay(100);
> - /*3 times*/
> - *sdram_addr = 0xff;
> - udelay(100);
> - /*4 times*/
> - *sdram_addr = 0xff;
> - udelay(100);
> - /*5 times*/
> - *sdram_addr = 0xff;
> - udelay(100);
> - /*6 times*/
> - *sdram_addr = 0xff;
> - udelay(100);
> - /*7 times*/
> - *sdram_addr = 0xff;
> - udelay(100);
> - /*8 times*/
> - *sdram_addr = 0xff;
> - udelay(100);
> -
> - /* 0x58636733; mode register write operation */
> - lbc->lsdmr = lsdmr_common | LSDMR_OP_MRW;
> - asm("sync");
> - *sdram_addr = 0xff;
> - udelay(100);
> -
> - /* 0x40636733; normal operation */
> - lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL;
> - asm("sync");
> - *sdram_addr = 0xff;
> - udelay(100);
> -}
> -#else
> -void sdram_init(void)
> -{
> - puts(" SDRAM on Local Bus: Disabled in config\n");
> -}
> -#endif
> -
> -#if defined(CONFIG_OF_BOARD_SETUP)
> -int ft_board_setup(void *blob, struct bd_info *bd)
> -{
> - ft_cpu_setup(blob, bd);
> -#ifdef CONFIG_PCI
> - ft_pci_setup(blob, bd);
> -#endif
> -
> - return 0;
> -}
> -#endif
> diff --git a/configs/sbc8349_PCI_33_defconfig b/configs/sbc8349_PCI_33_defconfig
> deleted file mode 100644
> index e428933b41e5..000000000000
> --- a/configs/sbc8349_PCI_33_defconfig
> +++ /dev/null
> @@ -1,123 +0,0 @@
> -CONFIG_PPC=y
> -CONFIG_SYS_TEXT_BASE=0xFF800000
> -CONFIG_ENV_SIZE=0x2000
> -CONFIG_ENV_SECT_SIZE=0x20000
> -CONFIG_SYS_CLK_FREQ=33000000
> -CONFIG_MPC83xx=y
> -CONFIG_HIGH_BATS=y
> -CONFIG_TARGET_SBC8349=y
> -CONFIG_DDR_MC_CLOCK_MODE_1_1=y
> -CONFIG_SYSTEM_PLL_FACTOR_8_1=y
> -CONFIG_CORE_PLL_RATIO_2_1=y
> -CONFIG_PCI_HOST_MODE_ENABLE=y
> -CONFIG_PCI_64BIT_MODE_ENABLE=y
> -CONFIG_PCI_INT_ARBITER1_ENABLE=y
> -CONFIG_BOOT_MEMORY_SPACE_LOW=y
> -CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
> -CONFIG_TSEC1_MODE_GMII=y
> -CONFIG_TSEC2_MODE_GMII=y
> -CONFIG_BAT0=y
> -CONFIG_BAT0_NAME="SDRAM"
> -CONFIG_BAT0_BASE=0x00000000
> -CONFIG_BAT0_LENGTH_256_MBYTES=y
> -CONFIG_BAT0_ACCESS_RW=y
> -CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y
> -CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y
> -CONFIG_BAT0_USER_MODE_VALID=y
> -CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
> -CONFIG_BAT1=y
> -CONFIG_BAT1_NAME="PCI1_MEM"
> -CONFIG_BAT1_BASE=0x80000000
> -CONFIG_BAT1_LENGTH_256_MBYTES=y
> -CONFIG_BAT1_ACCESS_RW=y
> -CONFIG_BAT1_ICACHE_MEMORYCOHERENCE=y
> -CONFIG_BAT1_DCACHE_MEMORYCOHERENCE=y
> -CONFIG_BAT1_USER_MODE_VALID=y
> -CONFIG_BAT1_SUPERVISOR_MODE_VALID=y
> -CONFIG_BAT2=y
> -CONFIG_BAT2_NAME="PCI1_MMIO"
> -CONFIG_BAT2_BASE=0x90000000
> -CONFIG_BAT2_LENGTH_256_MBYTES=y
> -CONFIG_BAT2_ACCESS_RW=y
> -CONFIG_BAT2_ICACHE_INHIBITED=y
> -CONFIG_BAT2_ICACHE_GUARDED=y
> -CONFIG_BAT2_DCACHE_INHIBITED=y
> -CONFIG_BAT2_DCACHE_GUARDED=y
> -CONFIG_BAT2_USER_MODE_VALID=y
> -CONFIG_BAT2_SUPERVISOR_MODE_VALID=y
> -CONFIG_BAT5=y
> -CONFIG_BAT5_NAME="IMMR_PCIIO"
> -CONFIG_BAT5_BASE=0xE0000000
> -CONFIG_BAT5_LENGTH_256_MBYTES=y
> -CONFIG_BAT5_ACCESS_RW=y
> -CONFIG_BAT5_ICACHE_INHIBITED=y
> -CONFIG_BAT5_ICACHE_GUARDED=y
> -CONFIG_BAT5_DCACHE_INHIBITED=y
> -CONFIG_BAT5_DCACHE_GUARDED=y
> -CONFIG_BAT5_USER_MODE_VALID=y
> -CONFIG_BAT5_SUPERVISOR_MODE_VALID=y
> -CONFIG_BAT6=y
> -CONFIG_BAT6_NAME="LBC_INITRAM_FLASH"
> -CONFIG_BAT6_BASE=0xF0000000
> -CONFIG_BAT6_LENGTH_256_MBYTES=y
> -CONFIG_BAT6_ACCESS_RW=y
> -CONFIG_BAT6_ICACHE_MEMORYCOHERENCE=y
> -CONFIG_BAT6_ICACHE_GUARDED=y
> -CONFIG_BAT6_DCACHE_MEMORYCOHERENCE=y
> -CONFIG_BAT6_DCACHE_GUARDED=y
> -CONFIG_BAT6_USER_MODE_VALID=y
> -CONFIG_BAT6_SUPERVISOR_MODE_VALID=y
> -CONFIG_LBLAW0=y
> -CONFIG_LBLAW0_BASE=0xFF800000
> -CONFIG_LBLAW0_NAME="FLASH"
> -CONFIG_LBLAW0_LENGTH_8_MBYTES=y
> -CONFIG_ELBC_BR0_OR0=y
> -CONFIG_BR0_OR0_NAME="FLASH"
> -CONFIG_BR0_OR0_BASE=0xFF800000
> -CONFIG_BR0_PORTSIZE_16BIT=y
> -CONFIG_OR0_AM_8_MBYTES=y
> -CONFIG_OR0_XAM_SET=y
> -CONFIG_OR0_SCY_15=y
> -CONFIG_OR0_CSNT_EARLIER=y
> -CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
> -CONFIG_OR0_XACS_EXTENDED=y
> -CONFIG_OR0_TRLX_RELAXED=y
> -CONFIG_OR0_EHTR_8_CYCLE=y
> -CONFIG_OR0_EAD_EXTRA=y
> -CONFIG_HID0_FINAL_EMCP=y
> -CONFIG_HID0_FINAL_ICE=y
> -CONFIG_HID2_HBE=y
> -CONFIG_LCRR_DBYP_PLL_BYPASSED=y
> -CONFIG_LCRR_CLKDIV_4=y
> -CONFIG_PCI_64BIT=y
> -CONFIG_OF_BOARD_SETUP=y
> -CONFIG_OF_STDOUT_VIA_ALIAS=y
> -CONFIG_SYS_EXTRA_OPTIONS="PCI_33M"
> -CONFIG_BOOTDELAY=6
> -CONFIG_HUSH_PARSER=y
> -CONFIG_CMD_IMLS=y
> -CONFIG_CMD_I2C=y
> -CONFIG_CMD_PCI=y
> -# CONFIG_CMD_SETEXPR is not set
> -CONFIG_CMD_MII=y
> -CONFIG_CMD_PING=y
> -CONFIG_ENV_OVERWRITE=y
> -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
> -CONFIG_ENV_ADDR=0xFF840000
> -CONFIG_ENV_ADDR_REDUND=0xFF860000
> -# CONFIG_MMC is not set
> -CONFIG_MTD_NOR_FLASH=y
> -CONFIG_FLASH_CFI_DRIVER=y
> -CONFIG_SYS_FLASH_CFI=y
> -CONFIG_PHY_ATHEROS=y
> -CONFIG_PHY_BROADCOM=y
> -CONFIG_PHY_DAVICOM=y
> -CONFIG_PHY_LXT=y
> -CONFIG_PHY_MARVELL=y
> -CONFIG_PHY_NATSEMI=y
> -CONFIG_PHY_REALTEK=y
> -CONFIG_PHY_SMSC=y
> -CONFIG_PHY_VITESSE=y
> -CONFIG_TSEC_ENET=y
> -CONFIG_SYS_NS16550=y
> -CONFIG_OF_LIBFDT=y
> diff --git a/configs/sbc8349_PCI_66_defconfig b/configs/sbc8349_PCI_66_defconfig
> deleted file mode 100644
> index 4774cd9836fe..000000000000
> --- a/configs/sbc8349_PCI_66_defconfig
> +++ /dev/null
> @@ -1,123 +0,0 @@
> -CONFIG_PPC=y
> -CONFIG_SYS_TEXT_BASE=0xFF800000
> -CONFIG_ENV_SIZE=0x2000
> -CONFIG_ENV_SECT_SIZE=0x20000
> -CONFIG_SYS_CLK_FREQ=66000000
> -CONFIG_MPC83xx=y
> -CONFIG_HIGH_BATS=y
> -CONFIG_TARGET_SBC8349=y
> -CONFIG_DDR_MC_CLOCK_MODE_1_1=y
> -CONFIG_SYSTEM_PLL_FACTOR_4_1=y
> -CONFIG_CORE_PLL_RATIO_2_1=y
> -CONFIG_PCI_HOST_MODE_ENABLE=y
> -CONFIG_PCI_64BIT_MODE_ENABLE=y
> -CONFIG_PCI_INT_ARBITER1_ENABLE=y
> -CONFIG_BOOT_MEMORY_SPACE_LOW=y
> -CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
> -CONFIG_TSEC1_MODE_GMII=y
> -CONFIG_TSEC2_MODE_GMII=y
> -CONFIG_BAT0=y
> -CONFIG_BAT0_NAME="SDRAM"
> -CONFIG_BAT0_BASE=0x00000000
> -CONFIG_BAT0_LENGTH_256_MBYTES=y
> -CONFIG_BAT0_ACCESS_RW=y
> -CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y
> -CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y
> -CONFIG_BAT0_USER_MODE_VALID=y
> -CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
> -CONFIG_BAT1=y
> -CONFIG_BAT1_NAME="PCI1_MEM"
> -CONFIG_BAT1_BASE=0x80000000
> -CONFIG_BAT1_LENGTH_256_MBYTES=y
> -CONFIG_BAT1_ACCESS_RW=y
> -CONFIG_BAT1_ICACHE_MEMORYCOHERENCE=y
> -CONFIG_BAT1_DCACHE_MEMORYCOHERENCE=y
> -CONFIG_BAT1_USER_MODE_VALID=y
> -CONFIG_BAT1_SUPERVISOR_MODE_VALID=y
> -CONFIG_BAT2=y
> -CONFIG_BAT2_NAME="PCI1_MMIO"
> -CONFIG_BAT2_BASE=0x90000000
> -CONFIG_BAT2_LENGTH_256_MBYTES=y
> -CONFIG_BAT2_ACCESS_RW=y
> -CONFIG_BAT2_ICACHE_INHIBITED=y
> -CONFIG_BAT2_ICACHE_GUARDED=y
> -CONFIG_BAT2_DCACHE_INHIBITED=y
> -CONFIG_BAT2_DCACHE_GUARDED=y
> -CONFIG_BAT2_USER_MODE_VALID=y
> -CONFIG_BAT2_SUPERVISOR_MODE_VALID=y
> -CONFIG_BAT5=y
> -CONFIG_BAT5_NAME="IMMR_PCIIO"
> -CONFIG_BAT5_BASE=0xE0000000
> -CONFIG_BAT5_LENGTH_256_MBYTES=y
> -CONFIG_BAT5_ACCESS_RW=y
> -CONFIG_BAT5_ICACHE_INHIBITED=y
> -CONFIG_BAT5_ICACHE_GUARDED=y
> -CONFIG_BAT5_DCACHE_INHIBITED=y
> -CONFIG_BAT5_DCACHE_GUARDED=y
> -CONFIG_BAT5_USER_MODE_VALID=y
> -CONFIG_BAT5_SUPERVISOR_MODE_VALID=y
> -CONFIG_BAT6=y
> -CONFIG_BAT6_NAME="LBC_INITRAM_FLASH"
> -CONFIG_BAT6_BASE=0xF0000000
> -CONFIG_BAT6_LENGTH_256_MBYTES=y
> -CONFIG_BAT6_ACCESS_RW=y
> -CONFIG_BAT6_ICACHE_MEMORYCOHERENCE=y
> -CONFIG_BAT6_ICACHE_GUARDED=y
> -CONFIG_BAT6_DCACHE_MEMORYCOHERENCE=y
> -CONFIG_BAT6_DCACHE_GUARDED=y
> -CONFIG_BAT6_USER_MODE_VALID=y
> -CONFIG_BAT6_SUPERVISOR_MODE_VALID=y
> -CONFIG_LBLAW0=y
> -CONFIG_LBLAW0_BASE=0xFF800000
> -CONFIG_LBLAW0_NAME="FLASH"
> -CONFIG_LBLAW0_LENGTH_8_MBYTES=y
> -CONFIG_ELBC_BR0_OR0=y
> -CONFIG_BR0_OR0_NAME="FLASH"
> -CONFIG_BR0_OR0_BASE=0xFF800000
> -CONFIG_BR0_PORTSIZE_16BIT=y
> -CONFIG_OR0_AM_8_MBYTES=y
> -CONFIG_OR0_XAM_SET=y
> -CONFIG_OR0_SCY_15=y
> -CONFIG_OR0_CSNT_EARLIER=y
> -CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
> -CONFIG_OR0_XACS_EXTENDED=y
> -CONFIG_OR0_TRLX_RELAXED=y
> -CONFIG_OR0_EHTR_8_CYCLE=y
> -CONFIG_OR0_EAD_EXTRA=y
> -CONFIG_HID0_FINAL_EMCP=y
> -CONFIG_HID0_FINAL_ICE=y
> -CONFIG_HID2_HBE=y
> -CONFIG_LCRR_DBYP_PLL_BYPASSED=y
> -CONFIG_LCRR_CLKDIV_4=y
> -CONFIG_PCI_64BIT=y
> -CONFIG_OF_BOARD_SETUP=y
> -CONFIG_OF_STDOUT_VIA_ALIAS=y
> -CONFIG_SYS_EXTRA_OPTIONS="PCI_66M"
> -CONFIG_BOOTDELAY=6
> -CONFIG_HUSH_PARSER=y
> -CONFIG_CMD_IMLS=y
> -CONFIG_CMD_I2C=y
> -CONFIG_CMD_PCI=y
> -# CONFIG_CMD_SETEXPR is not set
> -CONFIG_CMD_MII=y
> -CONFIG_CMD_PING=y
> -CONFIG_ENV_OVERWRITE=y
> -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
> -CONFIG_ENV_ADDR=0xFF840000
> -CONFIG_ENV_ADDR_REDUND=0xFF860000
> -# CONFIG_MMC is not set
> -CONFIG_MTD_NOR_FLASH=y
> -CONFIG_FLASH_CFI_DRIVER=y
> -CONFIG_SYS_FLASH_CFI=y
> -CONFIG_PHY_ATHEROS=y
> -CONFIG_PHY_BROADCOM=y
> -CONFIG_PHY_DAVICOM=y
> -CONFIG_PHY_LXT=y
> -CONFIG_PHY_MARVELL=y
> -CONFIG_PHY_NATSEMI=y
> -CONFIG_PHY_REALTEK=y
> -CONFIG_PHY_SMSC=y
> -CONFIG_PHY_VITESSE=y
> -CONFIG_TSEC_ENET=y
> -CONFIG_SYS_NS16550=y
> -CONFIG_OF_LIBFDT=y
> diff --git a/configs/sbc8349_defconfig b/configs/sbc8349_defconfig
> deleted file mode 100644
> index b69e66b61e1b..000000000000
> --- a/configs/sbc8349_defconfig
> +++ /dev/null
> @@ -1,101 +0,0 @@
> -CONFIG_PPC=y
> -CONFIG_SYS_TEXT_BASE=0xFF800000
> -CONFIG_ENV_SIZE=0x2000
> -CONFIG_ENV_SECT_SIZE=0x20000
> -CONFIG_SYS_CLK_FREQ=66000000
> -CONFIG_MPC83xx=y
> -CONFIG_HIGH_BATS=y
> -CONFIG_TARGET_SBC8349=y
> -CONFIG_DDR_MC_CLOCK_MODE_1_1=y
> -CONFIG_SYSTEM_PLL_FACTOR_4_1=y
> -CONFIG_CORE_PLL_RATIO_2_1=y
> -CONFIG_PCI_HOST_MODE_ENABLE=y
> -CONFIG_PCI_INT_ARBITER1_ENABLE=y
> -CONFIG_PCI_INT_ARBITER2_ENABLE=y
> -CONFIG_BOOT_MEMORY_SPACE_LOW=y
> -CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
> -CONFIG_TSEC1_MODE_GMII=y
> -CONFIG_TSEC2_MODE_GMII=y
> -CONFIG_BAT0=y
> -CONFIG_BAT0_NAME="SDRAM"
> -CONFIG_BAT0_BASE=0x00000000
> -CONFIG_BAT0_LENGTH_256_MBYTES=y
> -CONFIG_BAT0_ACCESS_RW=y
> -CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y
> -CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y
> -CONFIG_BAT0_USER_MODE_VALID=y
> -CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
> -CONFIG_BAT5=y
> -CONFIG_BAT5_NAME="IMMR_PCIIO"
> -CONFIG_BAT5_BASE=0xE0000000
> -CONFIG_BAT5_LENGTH_256_MBYTES=y
> -CONFIG_BAT5_ACCESS_RW=y
> -CONFIG_BAT5_ICACHE_INHIBITED=y
> -CONFIG_BAT5_ICACHE_GUARDED=y
> -CONFIG_BAT5_DCACHE_INHIBITED=y
> -CONFIG_BAT5_DCACHE_GUARDED=y
> -CONFIG_BAT5_USER_MODE_VALID=y
> -CONFIG_BAT5_SUPERVISOR_MODE_VALID=y
> -CONFIG_BAT6=y
> -CONFIG_BAT6_NAME="LBC_INITRAM_FLASH"
> -CONFIG_BAT6_BASE=0xF0000000
> -CONFIG_BAT6_LENGTH_256_MBYTES=y
> -CONFIG_BAT6_ACCESS_RW=y
> -CONFIG_BAT6_ICACHE_MEMORYCOHERENCE=y
> -CONFIG_BAT6_ICACHE_GUARDED=y
> -CONFIG_BAT6_DCACHE_MEMORYCOHERENCE=y
> -CONFIG_BAT6_DCACHE_GUARDED=y
> -CONFIG_BAT6_USER_MODE_VALID=y
> -CONFIG_BAT6_SUPERVISOR_MODE_VALID=y
> -CONFIG_LBLAW0=y
> -CONFIG_LBLAW0_BASE=0xFF800000
> -CONFIG_LBLAW0_NAME="FLASH"
> -CONFIG_LBLAW0_LENGTH_8_MBYTES=y
> -CONFIG_ELBC_BR0_OR0=y
> -CONFIG_BR0_OR0_NAME="FLASH"
> -CONFIG_BR0_OR0_BASE=0xFF800000
> -CONFIG_BR0_PORTSIZE_16BIT=y
> -CONFIG_OR0_AM_8_MBYTES=y
> -CONFIG_OR0_XAM_SET=y
> -CONFIG_OR0_SCY_15=y
> -CONFIG_OR0_CSNT_EARLIER=y
> -CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
> -CONFIG_OR0_XACS_EXTENDED=y
> -CONFIG_OR0_TRLX_RELAXED=y
> -CONFIG_OR0_EHTR_8_CYCLE=y
> -CONFIG_OR0_EAD_EXTRA=y
> -CONFIG_HID0_FINAL_EMCP=y
> -CONFIG_HID0_FINAL_ICE=y
> -CONFIG_HID2_HBE=y
> -CONFIG_LCRR_DBYP_PLL_BYPASSED=y
> -CONFIG_LCRR_CLKDIV_4=y
> -CONFIG_OF_BOARD_SETUP=y
> -CONFIG_OF_STDOUT_VIA_ALIAS=y
> -CONFIG_BOOTDELAY=6
> -CONFIG_HUSH_PARSER=y
> -CONFIG_CMD_IMLS=y
> -CONFIG_CMD_I2C=y
> -# CONFIG_CMD_SETEXPR is not set
> -CONFIG_CMD_MII=y
> -CONFIG_CMD_PING=y
> -CONFIG_ENV_OVERWRITE=y
> -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
> -CONFIG_ENV_ADDR=0xFF840000
> -CONFIG_ENV_ADDR_REDUND=0xFF860000
> -# CONFIG_MMC is not set
> -CONFIG_MTD_NOR_FLASH=y
> -CONFIG_FLASH_CFI_DRIVER=y
> -CONFIG_SYS_FLASH_CFI=y
> -CONFIG_PHY_ATHEROS=y
> -CONFIG_PHY_BROADCOM=y
> -CONFIG_PHY_DAVICOM=y
> -CONFIG_PHY_LXT=y
> -CONFIG_PHY_MARVELL=y
> -CONFIG_PHY_NATSEMI=y
> -CONFIG_PHY_REALTEK=y
> -CONFIG_PHY_SMSC=y
> -CONFIG_PHY_VITESSE=y
> -CONFIG_TSEC_ENET=y
> -# CONFIG_PCI is not set
> -CONFIG_SYS_NS16550=y
> -CONFIG_OF_LIBFDT=y
> diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h
> deleted file mode 100644
> index 929579efe133..000000000000
> --- a/include/configs/sbc8349.h
> +++ /dev/null
> @@ -1,322 +0,0 @@
> -/* SPDX-License-Identifier: GPL-2.0+ */
> -/*
> - * WindRiver SBC8349 U-Boot configuration file.
> - * Copyright (c) 2006, 2007 Wind River Systems, Inc.
> - *
> - * Paul Gortmaker <paul.gortmaker@windriver.com>
> - * Based on the MPC8349EMDS config.
> - */
> -
> -/*
> - * sbc8349 board configuration file.
> - */
> -
> -#ifndef __CONFIG_H
> -#define __CONFIG_H
> -
> -/*
> - * High Level Configuration Options
> - */
> -#define CONFIG_E300 1 /* E300 Family */
> -
> -/* Don't enable PCI2 on sbc834x - it doesn't exist physically. */
> -#undef CONFIG_MPC83XX_PCI2 /* support for 2nd PCI controller */
> -
> -#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
> -
> -/*
> - * DDR Setup
> - */
> -#undef CONFIG_DDR_ECC /* only for ECC DDR module */
> -#undef CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */
> -#define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/
> -#define CONFIG_SYS_83XX_DDR_USES_CS0 /* WRS; Fsl board uses CS2/CS3 */
> -
> -/*
> - * 32-bit data path mode.
> - *
> - * Please note that using this mode for devices with the real density of 64-bit
> - * effectively reduces the amount of available memory due to the effect of
> - * wrapping around while translating address to row/columns, for example in the
> - * 256MB module the upper 128MB get aliased with contents of the lower
> - * 128MB); normally this define should be used for devices with real 32-bit
> - * data path.
> - */
> -#undef CONFIG_DDR_32BIT
> -
> -#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory*/
> -#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \
> - DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)
> -#define CONFIG_DDR_2T_TIMING
> -
> -#if defined(CONFIG_SPD_EEPROM)
> -/*
> - * Determine DDR configuration from I2C interface.
> - */
> -#define SPD_EEPROM_ADDRESS 0x52 /* DDR DIMM */
> -
> -#else
> -/*
> - * Manually set up DDR parameters
> - * NB: manual DDR setup untested on sbc834x
> - */
> -#define CONFIG_SYS_DDR_SIZE 256 /* MB */
> -#define CONFIG_SYS_DDR_CS2_CONFIG (CSCONFIG_EN \
> - | CSCONFIG_ROW_BIT_13 \
> - | CSCONFIG_COL_BIT_10)
> -#define CONFIG_SYS_DDR_TIMING_1 0x36332321
> -#define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */
> -#define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */
> -#define CONFIG_SYS_DDR_INTERVAL 0x04060100 /* autocharge,no open page */
> -
> -#if defined(CONFIG_DDR_32BIT)
> -/* set burst length to 8 for 32-bit data path */
> - /* DLL,normal,seq,4/2.5, 8 burst len */
> -#define CONFIG_SYS_DDR_MODE 0x00000023
> -#else
> -/* the default burst length is 4 - for 64-bit data path */
> - /* DLL,normal,seq,4/2.5, 4 burst len */
> -#define CONFIG_SYS_DDR_MODE 0x00000022
> -#endif
> -#endif
> -
> -/*
> - * SDRAM on the Local Bus
> - */
> -#define CONFIG_SYS_LBC_SDRAM_BASE 0xF0000000 /* Localbus SDRAM */
> -#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
> -
> -/*
> - * FLASH on the Local Bus
> - */
> -#define CONFIG_SYS_FLASH_BASE 0xFF800000 /* start of FLASH */
> -#define CONFIG_SYS_FLASH_SIZE 8 /* flash size in MB */
> -
> -
> -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
> -#define CONFIG_SYS_MAX_FLASH_SECT 64 /* sectors per device */
> -
> -#undef CONFIG_SYS_FLASH_CHECKSUM
> -#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
> -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
> -
> -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
> -
> -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
> -#define CONFIG_SYS_RAMBOOT
> -#else
> -#undef CONFIG_SYS_RAMBOOT
> -#endif
> -
> -#define CONFIG_SYS_INIT_RAM_LOCK 1
> - /* Initial RAM address */
> -#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000
> - /* Size of used area in RAM*/
> -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
> -
> -#define CONFIG_SYS_GBL_DATA_OFFSET \
> - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
> -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
> -
> -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
> -#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */
> -
> -#undef CONFIG_SYS_LB_SDRAM /* if board has SDRAM on local bus */
> -
> -/*
> - * Serial Port
> - */
> -#define CONFIG_SYS_NS16550_SERIAL
> -#define CONFIG_SYS_NS16550_REG_SIZE 1
> -#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
> -
> -#define CONFIG_SYS_BAUDRATE_TABLE \
> - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
> -
> -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
> -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
> -
> -/* I2C */
> -#define CONFIG_SYS_I2C
> -#define CONFIG_SYS_I2C_FSL
> -#define CONFIG_SYS_FSL_I2C_SPEED 400000
> -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
> -#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
> -#define CONFIG_SYS_FSL_I2C2_SPEED 400000
> -#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
> -#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
> -#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69}, {1, 0x69} }
> -/* could also use CONFIG_I2C_MULTI_BUS and CONFIG_SYS_SPD_BUS_NUM... */
> -
> -/* TSEC */
> -#define CONFIG_SYS_TSEC1_OFFSET 0x24000
> -#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
> -#define CONFIG_SYS_TSEC2_OFFSET 0x25000
> -#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
> -
> -/*
> - * General PCI
> - * Addresses are mapped 1-1.
> - */
> -#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
> -#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
> -#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
> -#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
> -#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
> -#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
> -#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
> -#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
> -#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
> -
> -#define CONFIG_SYS_PCI2_MEM_BASE 0xA0000000
> -#define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE
> -#define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */
> -#define CONFIG_SYS_PCI2_MMIO_BASE 0xB0000000
> -#define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE
> -#define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */
> -#define CONFIG_SYS_PCI2_IO_BASE 0x00000000
> -#define CONFIG_SYS_PCI2_IO_PHYS 0xE2100000
> -#define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */
> -
> -#if defined(CONFIG_PCI)
> -
> -
> -#if !defined(CONFIG_PCI_PNP)
> - #define PCI_ENET0_IOADDR 0xFIXME
> - #define PCI_ENET0_MEMADDR 0xFIXME
> - #define PCI_IDSEL_NUMBER 0xFIXME
> -#endif
> -
> -#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
> -#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
> -
> -#endif /* CONFIG_PCI */
> -
> -/*
> - * TSEC configuration
> - */
> -
> -#if defined(CONFIG_TSEC_ENET)
> -
> -#define CONFIG_TSEC1 1
> -#define CONFIG_TSEC1_NAME "TSEC0"
> -#define CONFIG_TSEC2 1
> -#define CONFIG_TSEC2_NAME "TSEC1"
> -#define CONFIG_PHY_BCM5421S 1
> -#define TSEC1_PHY_ADDR 0x19
> -#define TSEC2_PHY_ADDR 0x1a
> -#define TSEC1_PHYIDX 0
> -#define TSEC2_PHYIDX 0
> -#define TSEC1_FLAGS TSEC_GIGABIT
> -#define TSEC2_FLAGS TSEC_GIGABIT
> -
> -/* Options are: TSEC[0-1] */
> -#define CONFIG_ETHPRIME "TSEC0"
> -
> -#endif /* CONFIG_TSEC_ENET */
> -
> -/*
> - * Environment
> - */
> -#ifndef CONFIG_SYS_RAMBOOT
> -/* Address and size of Redundant Environment Sector */
> -#endif
> -
> -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
> -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
> -
> -/*
> - * BOOTP options
> - */
> -#define CONFIG_BOOTP_BOOTFILESIZE
> -
> -#undef CONFIG_WATCHDOG /* watchdog disabled */
> -
> -/*
> - * Miscellaneous configurable options
> - */
> -#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
> -
> -/*
> - * For booting Linux, the board info and command line data
> - * have to be in the first 256 MB of memory, since this is
> - * the maximum mapped by the Linux kernel during initialization.
> - */
> - /* Initial Memory map for Linux*/
> -#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
> -
> -#define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */
> -
> -/* System IO Config */
> -#define CONFIG_SYS_SICRH 0
> -#define CONFIG_SYS_SICRL SICRL_LDP_A
> -
> -#ifdef CONFIG_PCI
> -#define CONFIG_PCI_INDIRECT_BRIDGE
> -#endif
> -
> -#if defined(CONFIG_CMD_KGDB)
> -#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
> -#endif
> -
> -/*
> - * Environment Configuration
> - */
> -
> -#if defined(CONFIG_TSEC_ENET)
> -#define CONFIG_HAS_ETH0
> -#define CONFIG_HAS_ETH1
> -#endif
> -
> -#define CONFIG_HOSTNAME "SBC8349"
> -#define CONFIG_ROOTPATH "/tftpboot/rootfs"
> -#define CONFIG_BOOTFILE "uImage"
> -
> - /* default location for tftp and bootm */
> -#define CONFIG_LOADADDR 800000
> -
> -#define CONFIG_EXTRA_ENV_SETTINGS \
> - "netdev=eth0\0" \
> - "hostname=sbc8349\0" \
> - "nfsargs=setenv bootargs root=/dev/nfs rw " \
> - "nfsroot=${serverip}:${rootpath}\0" \
> - "ramargs=setenv bootargs root=/dev/ram rw\0" \
> - "addip=setenv bootargs ${bootargs} " \
> - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
> - ":${hostname}:${netdev}:off panic=1\0" \
> - "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
> - "flash_nfs=run nfsargs addip addtty;" \
> - "bootm ${kernel_addr}\0" \
> - "flash_self=run ramargs addip addtty;" \
> - "bootm ${kernel_addr} ${ramdisk_addr}\0" \
> - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
> - "bootm\0" \
> - "load=tftp 100000 /tftpboot/sbc8349/u-boot.bin\0" \
> - "update=protect off ff800000 ff83ffff; " \
> - "era ff800000 ff83ffff; cp.b 100000 ff800000 ${filesize}\0" \
> - "upd=run load update\0" \
> - "fdtaddr=780000\0" \
> - "fdtfile=sbc8349.dtb\0" \
> - ""
> -
> -#define CONFIG_NFSBOOTCOMMAND \
> - "setenv bootargs root=/dev/nfs rw " \
> - "nfsroot=$serverip:$rootpath " \
> - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \
> - "$netdev:off " \
> - "console=$consoledev,$baudrate $othbootargs;" \
> - "tftp $loadaddr $bootfile;" \
> - "tftp $fdtaddr $fdtfile;" \
> - "bootm $loadaddr - $fdtaddr"
> -
> -#define CONFIG_RAMBOOTCOMMAND \
> - "setenv bootargs root=/dev/ram rw " \
> - "console=$consoledev,$baudrate $othbootargs;" \
> - "tftp $ramdiskaddr $ramdiskfile;" \
> - "tftp $loadaddr $bootfile;" \
> - "tftp $fdtaddr $fdtfile;" \
> - "bootm $loadaddr $ramdiskaddr $fdtaddr"
> -
> -#define CONFIG_BOOTCOMMAND "run flash_self"
> -
> -#endif /* __CONFIG_H */
> --
> 2.17.1
>