From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-19.4 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 542EEC47082 for ; Wed, 26 May 2021 16:01:20 +0000 (UTC) Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 6FD5C613AC for ; Wed, 26 May 2021 16:01:19 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 6FD5C613AC Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=kernel.org Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id DEF6A82E45; Wed, 26 May 2021 18:01:06 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=kernel.org header.i=@kernel.org header.b="CtdS6gdi"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 0584882ED5; Wed, 26 May 2021 18:00:54 +0200 (CEST) Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id D987E82E3C for ; Wed, 26 May 2021 18:00:45 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=pali@kernel.org Received: by mail.kernel.org (Postfix) with ESMTPSA id 52FC8613DE; Wed, 26 May 2021 16:00:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1622044844; bh=P/I9JAFBtYSM6wNdZYtg3ZKroHgSvU/CJHFXG/Ipwvk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=CtdS6gdiHvbD06najIY/Sq3UJ+CbolgDcEJAB8Womalh2QtMj8hU1S5I13eCCmmCa nA85dp7K8xGei5oZ+xy5ZGbq7YUrs/wf69TVy5vsxNv8vzFwWv4zkavEnmkL8wqmta z0wG95tqB6ALRByCEi4/TQrK0nMcsLyoTdEcq4rkSXzFmJJujLBayYHhmsDnD5rNfw iGg5+nXAKNi1QtPQZo9WCFRsj3Xz/YLuB/jH9IuzErMkGkYgK/GXCVGSbzcM7SlMBM VmdUSNbzgM0jRhr1uP/55dDdYr0maiqXiUet7YWkOKjST53+0Pyr86fb7qf/lUGbcn MBwEWqmgyNvZg== Received: by pali.im (Postfix) id 985AEC77; Wed, 26 May 2021 18:00:43 +0200 (CEST) From: =?UTF-8?q?Pali=20Roh=C3=A1r?= To: Stefan Roese , Konstantin Porotchkin Cc: =?UTF-8?q?Marek=20Beh=C3=BAn?= , u-boot@lists.denx.de Subject: [PATCH v2 6/7] arm: a37xx: pci: Increase PCIe MEM size from 16 MiB to 127 MiB Date: Wed, 26 May 2021 17:59:39 +0200 Message-Id: <20210526155940.26141-6-pali@kernel.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210526155940.26141-1-pali@kernel.org> References: <20210517063956.30905-1-pali@kernel.org> <20210526155940.26141-1-pali@kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.4 at phobos.denx.de X-Virus-Status: Clean For some configurations with more PCIe cards and PCIe bridges, 16 MiB of PCIe MEM space may not be enough. Since TF-A already allocates a 128 MiB CPU window for PCIe, and since IO port space is only 64 KiB in total, use all the remaining space (64 + 32 + 16 + 8 + 4 + 2 + 1 = 127 MiB) for PCIe MEM. Signed-off-by: Pali Rohár Reviewed-by: Marek Behún --- Changes in v2: * Fix size for PCIe MEM --- arch/arm/dts/armada-37xx.dtsi | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/arch/arm/dts/armada-37xx.dtsi b/arch/arm/dts/armada-37xx.dtsi index b7d325b40577..2615b8c748c1 100644 --- a/arch/arm/dts/armada-37xx.dtsi +++ b/arch/arm/dts/armada-37xx.dtsi @@ -332,10 +332,17 @@ status = "disabled"; bus-range = <0 0xff>; + /* + * The 128 MiB address range [0xe8000000-0xf0000000] is + * dedicated for PCIe and can be assigned to 8 windows + * with size a power of two. Use one 64 KiB window for + * IO at the end and the remaining seven windows + * (totaling 127 MiB) for MEM. + */ ranges = <0x82000000 0 0xe8000000 - 0 0xe8000000 0 0x1000000 /* Port 0 MEM */ - 0x81000000 0 0xe9000000 - 0 0xe9000000 0 0x10000>; /* Port 0 IO*/ + 0 0xe8000000 0 0x7f00000 /* Port 0 MEM */ + 0x81000000 0 0xefff0000 + 0 0xefff0000 0 0x10000>; /* Port 0 IO*/ }; }; }; -- 2.20.1