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Thu, 27 May 2021 08:58:46 +0000 (UTC) Date: Thu, 27 May 2021 10:58:45 +0200 From: Miquel Raynal To: Jaime Liao Cc: u-boot@lists.denx.de, jagan@amarulasolutions.com, vigneshr@ti.com, zhengxunli@mxic.com.tw, ycllin@mxic.com.tw Subject: Re: [PATCH] mtd: spinand: macronix: Add support for serial NAND flash Message-ID: <20210527105845.40447cd4@xps13> In-Reply-To: <1622105472-10532-1-git-send-email-jaimeliao@mxic.com.tw> References: <1622105472-10532-1-git-send-email-jaimeliao@mxic.com.tw> Organization: Bootlin X-Mailer: Claws Mail 3.17.7 (GTK+ 2.24.32; x86_64-pc-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.4 at phobos.denx.de X-Virus-Status: Clean Hi Jaime, Jaime Liao wrote on Thu, 27 May 2021 16:51:12 +0800: > Macronix NAND Flash devices are available in different configurations > and densities. >=20 > MX"35" means SPI NAND > MX35"LF"/"UF" , LF means 3V and UF meands 1.8V > MX35LF"2G" , 2G means 2Gbits > MX35LF2G"E4"/"24"/"14", > E4 means internal ECC and Quad I/O(x4) > 24 means 8-bit ecc requirement and Quad I/O(x4) > 14 means 4-bit ecc requirement and Quad I/O(x4) >=20 > MX35LF2G14AC is 3V 2Gbit serial NAND flash device > (without on-die ECC) > https://www.mxic.com.tw/Lists/Datasheet/Attachments/7926/MX35LF2G14AC,%20= 3V,%202Gb,%20v1.1.pdf >=20 > MX35UF4G24AD/MX35UF2G24AD/MX35UF1G24AD is 1.8V 4Gbit serial NAND flash de= vice > (without on-die ECC) > https://www.mxic.com.tw/Lists/Datasheet/Attachments/7980/MX35UF4G24AD,%20= 1.8V,%204Gb,%20v0.00.pdf >=20 > MX35UF4GE4AD/MX35UF2GE4AD/MX35UF1GE4AD are 1.8V 4G/2Gbit serial > NAND flash device with 8-bit on-die ECC > https://www.mxic.com.tw/Lists/Datasheet/Attachments/7983/MX35UF4GE4AD,%20= 1.8V,%204Gb,%20v0.00.pdf >=20 > MX35UF2GE4AC/MX35UF1GE4AC are 1.8V 2G/1Gbit serial > NAND flash device with 8-bit on-die ECC > https://www.mxic.com.tw/Lists/Datasheet/Attachments/7974/MX35UF2GE4AC,%20= 1.8V,%202Gb,%20v1.0.pdf >=20 > MX35UF2G14AC/MX35UF1G14AC are 1.8V 2G/1Gbit serial > NAND flash device (without on-die ECC) > https://www.mxic.com.tw/Lists/Datasheet/Attachments/7931/MX35UF2G14AC,%20= 1.8V,%202Gb,%20v1.1.pdf >=20 > Validated via normal(default) and QUAD mode by read, erase, read back, > on Xilinx Zynq PicoZed FPGA board which included Macronix > SPI Host(drivers/spi/spi-mxic.c). >=20 > Signed-off-by: Jaime Liao > --- > drivers/mtd/nand/spi/macronix.c | 100 ++++++++++++++++++++++++++++++++++= ++++++ > 1 file changed, 100 insertions(+) >=20 > diff --git a/drivers/mtd/nand/spi/macronix.c b/drivers/mtd/nand/spi/macro= nix.c > index 215f09a..8a33dce 100644 > --- a/drivers/mtd/nand/spi/macronix.c > +++ b/drivers/mtd/nand/spi/macronix.c > @@ -114,6 +114,106 @@ static const struct spinand_info macronix_spinand_t= able[] =3D { > &update_cache_variants), > SPINAND_HAS_QE_BIT, > SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, NULL)), > + SPINAND_INFO("MX35LF2G14AC", 0x20, > + NAND_MEMORG(1, 2048, 64, 64, 2048, 2, 1, 1), > + NAND_ECCREQ(4, 512), > + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, > + &write_cache_variants, > + &update_cache_variants), > + SPINAND_HAS_QE_BIT, > + SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, > + mx35lf1ge4ab_ecc_get_status)), This looks like a copy of your previous patch, with the SPINAND_ID macro dropped. It would be great if you could clarify your intentions when sending patches. This means: - Counting up patch versions - Explaining their differences and why So, what is the purpose of this patch give the fact that I already applied one very similar yesterday? Thanks, Miqu=C3=A8l