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Fri, 28 May 2021 13:49:43 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=denx.de; s=phobos-20191101; t=1622202584; bh=e39uiFpvH1Bge8J0RMxSvCElUOnKWMFubhyBQtEWRu4=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=PkSeYZrmvPzQ7DwthQaUIQA2cMjyaDIC9Ox/+nXkvco0CzVZBtDResVJUQo0PukVU Us55L0iYsgE01lmiUrio5zVUpaS6TGo29b8+J1adb6tg4uMN33mMP/ccP2qny08Du1 YkPXbgu5SvPYbfSfb7uwvqm+wsbwvmKzpssY727hPWDeuSfqOI9WIFBdqneqoblQgo ur9jnxSbDs+/Fe/CyfCZkMcUQCTdOEkRPNHbIy76GhNWt5PGr4qk0KNgmEL+7Cd9vw x7q8y3UxR5kprIngeJcEcit+miDf2nMLk9OqWwKhrI7HUKil+iHxrqHgBWvhPCHNzr /Q0hmNh8b9PeQ== Date: Fri, 28 May 2021 13:49:37 +0200 From: Lukasz Majewski To: Ramon Fried , U-Boot Mailing List , Joe Hershberger , Tom Rini Cc: Simon Glass Subject: Re: [PATCH v1 1/6] net: mv88e61xx: Add support for checking addressing mode Message-ID: <20210528134937.50ce7fb7@ktm> In-Reply-To: References: <20210317141410.32152-1-lukma@denx.de> <20210317141410.32152-2-lukma@denx.de> Organization: denx.de X-Mailer: Claws Mail 3.17.8 (GTK+ 2.24.32; x86_64-pc-linux-gnu) MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha512; boundary="Sig_/.bAy4HIsjOVk3iaI08Afpx4"; protocol="application/pgp-signature" X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.4 at phobos.denx.de X-Virus-Status: Clean --Sig_/.bAy4HIsjOVk3iaI08Afpx4 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: quoted-printable Hi Joe, Tom, > On Wed, Mar 17, 2021 at 4:14 PM Lukasz Majewski wrote: > > > > Some Marvell switch devices are dual chip ones, like mv88e6020, > > which use direct MDIO addressing to access its ports' registers. > > Such approach allows connecting two such devices in a single MDIO > > bus with simple addressing scheme. > > > > Signed-off-by: Lukasz Majewski > > --- > > > > drivers/net/phy/mv88e61xx.c | 42 > > +++++++++++++++++++++++++++++++++++++ 1 file changed, 42 > > insertions(+) > > > > diff --git a/drivers/net/phy/mv88e61xx.c > > b/drivers/net/phy/mv88e61xx.c index 7eff37b24499..69a1dd8f1859 > > 100644 --- a/drivers/net/phy/mv88e61xx.c > > +++ b/drivers/net/phy/mv88e61xx.c > > @@ -202,6 +202,7 @@ struct mv88e61xx_phy_priv { > > u8 phy_ctrl1_en_det_shift; /* 'EDet' bit field offset */ > > u8 phy_ctrl1_en_det_width; /* Width of 'EDet' bit field */ > > u8 phy_ctrl1_en_det_ctrl; /* 'EDet' control value */ > > + u8 direct_access; /* Access switch device directly > > */ }; > > > > static inline int smi_cmd(int cmd, int addr, int reg) > > @@ -928,6 +929,40 @@ static int > > mv88e61xx_priv_reg_offs_pre_init(struct phy_device *phydev) return > > -ENODEV; } > > > > +static int mv88e61xx_check_addressing(struct phy_device *phydev) > > +{ > > + if (!CONFIG_IS_ENABLED(OF_CONTROL)) > > + return 0; > > + > > + /* > > + * Some devices - like mv88e6020 are dual chip - i.e. two > > + * such devices can be directly accessed via SMI bus. > > + * The addressing depends on R0_LED/ADDR4 pin value duing > > + * bootstrap. > > + * > > + * This means that there is no need for indirect access. > > + */ > > + struct mv88e61xx_phy_priv *priv =3D phydev->priv; > > + > > + /* > > + * As this function is called very early and hence the > > phydev > > + * is not yet initialized we use aliast and DTS to asses if > > + * device shall be directly accessed or not. > > + */ > > + ofnode sw0; > > + int ret; > > + > > + sw0 =3D ofnode_get_aliases_node("switch0"); > > + if (!ofnode_valid(sw0)) > > + return -ENODEV; > > + > > + ret =3D ofnode_device_is_compatible(sw0, "marvell,mv88e6020"); > > + if (ret) > > + priv->direct_access =3D 1; > > + > > + return 0; > > +} > > + > > static int mv88e61xx_probe(struct phy_device *phydev) > > { > > struct mii_dev *smi_wrapper; > > @@ -982,6 +1017,8 @@ static int mv88e61xx_probe(struct phy_device > > *phydev) > > > > phydev->priv =3D priv; > > > > + mv88e61xx_check_addressing(phydev); > > + > > res =3D mv88e61xx_priv_reg_offs_pre_init(phydev); > > if (res < 0) > > return res; > > @@ -1197,6 +1234,11 @@ int get_phy_id(struct mii_dev *bus, int > > smi_addr, int devad, u32 *phy_id) temp_phy.priv =3D &temp_priv; > > temp_mii.priv =3D &temp_phy; > > > > + mv88e61xx_check_addressing(&temp_phy); > > + /* For direct access the phy address equals to smi_addr */ > > + if (temp_priv.direct_access) > > + temp_phy.addr =3D smi_addr; > > + > > /* > > * get_phy_id() can be called by framework before mv88e61xx > > driver > > * probing, in this case the global register offsets are not > > -- > > 2.20.1 > > =20 >=20 > Reviewed-by: Ramon Fried Could this patch series be pulled to u-boot-net tree (or directly to -master branch) ? Best regards, Lukasz Majewski -- DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lukma@denx.de --Sig_/.bAy4HIsjOVk3iaI08Afpx4 Content-Type: application/pgp-signature Content-Description: OpenPGP digital signature -----BEGIN PGP SIGNATURE----- iQEzBAEBCgAdFiEEgAyFJ+N6uu6+XupJAR8vZIA0zr0FAmCw2NEACgkQAR8vZIA0 zr3z0gf/d2lfOLMtXFWVTIFEfdGpWqNrPgXIFhtOe09qFEnCjREGZXG6OCXRtfHH 6TScbqkJQxMuMXcx+c+MrlmI7gVHffMrM2Gn7MN5wdAVsmCkUz5K+OFrK208m7F2 bCC3AJEbv5o5Xsn7fIvVp2C1L0yQPQuOsVv7hptLnLbNtFA82tlvKmeaJ9aTuJ/+ /WTQtBHQYz/8SFvGtiBLl6h+2YK/jB1OpsjVrhHVmJIbvR+L/332ALjWUUubFxe2 x55vMNqJZcXeLfinQWnSuxUizvB2GJTLMZWp/AxZpbCwIc//8WiacMfchqZZ1Sbu gpb8rrNNPDkx5gwzPZgjCoYf012wHQ== =7MI+ -----END PGP SIGNATURE----- --Sig_/.bAy4HIsjOVk3iaI08Afpx4--