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[74.96.87.9]) by smtp.gmail.com with ESMTPSA id s10sm3120612qkj.77.2021.06.03.20.58.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Jun 2021 20:58:43 -0700 (PDT) From: Sean Anderson To: u-boot@lists.denx.de Cc: Lukasz Majewski , Leo Liang , Damien Le Moal , Sean Anderson Subject: [PATCH v2 06/11] clk: k210: Don't set PLL rates if we are already at the correct rate Date: Thu, 3 Jun 2021 23:58:29 -0400 Message-Id: <20210604035834.625772-7-seanga2@gmail.com> X-Mailer: git-send-email 2.31.0 In-Reply-To: <20210604035834.625772-1-seanga2@gmail.com> References: <20210604035834.625772-1-seanga2@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.4 at phobos.denx.de X-Virus-Status: Clean This speeds up boot by preventing multiple reconfigurations of the PLLs. Signed-off-by: Sean Anderson --- (no changes since v1) drivers/clk/kendryte/clk.c | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/drivers/clk/kendryte/clk.c b/drivers/clk/kendryte/clk.c index a1742eb856..bb6d4a1692 100644 --- a/drivers/clk/kendryte/clk.c +++ b/drivers/clk/kendryte/clk.c @@ -847,21 +847,22 @@ static ulong k210_pll_set_rate(struct k210_clk_priv *priv, int id, ulong rate, const struct k210_pll_params *pll = &k210_plls[id]; struct k210_pll_config config = {}; u32 reg; + ulong calc_rate; if (rate_in < 0) return rate_in; - log_debug("Calculating parameters with rate=%lu and rate_in=%lu\n", - rate, rate_in); err = k210_pll_calc_config(rate, rate_in, &config); if (err) return err; log_debug("Got r=%u f=%u od=%u\n", config.r, config.f, config.od); - /* - * Don't use clk_disable as it might not actually disable the pll due to - * refcounting - */ + /* Don't bother setting the rate if we're already at that rate */ + calc_rate = DIV_ROUND_DOWN_ULL(((u64)rate_in) * config.f, + config.r * config.od); + if (calc_rate == k210_pll_get_rate(priv, id, rate)) + return calc_rate; + k210_pll_disable(priv, id); reg = readl(priv->base + pll->off); @@ -875,7 +876,7 @@ static ulong k210_pll_set_rate(struct k210_clk_priv *priv, int id, ulong rate, | FIELD_PREP(K210_PLL_BWADJ, config.f - 1); writel(reg, priv->base + pll->off); - err = k210_pll_enable(priv, id); + k210_pll_enable(priv, id); serial_setbrg(); return k210_pll_get_rate(priv, id, rate); -- 2.31.0