From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.2 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,INCLUDES_PULL_REQUEST, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 41ED7C48BE6 for ; Wed, 16 Jun 2021 07:44:29 +0000 (UTC) Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 1C0A561159 for ; Wed, 16 Jun 2021 07:44:27 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 1C0A561159 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=andestech.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id CA3C38164D; Wed, 16 Jun 2021 09:44:25 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=andestech.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id 4AA8782903; Wed, 16 Jun 2021 09:44:24 +0200 (CEST) Received: from ATCSQR.andestech.com (atcsqr.andestech.com [60.248.187.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id EC3CB81107 for ; Wed, 16 Jun 2021 09:44:19 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=andestech.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=ycliang@andestech.com Received: from mail.andestech.com (atcpcs16.andestech.com [10.0.1.222]) by ATCSQR.andestech.com with ESMTP id 15G7i1AD034363; Wed, 16 Jun 2021 15:44:01 +0800 (GMT-8) (envelope-from ycliang@andestech.com) Received: from andestech.com (10.0.15.65) by ATCPCS16.andestech.com (10.0.1.222) with Microsoft SMTP Server id 14.3.498.0; Wed, 16 Jun 2021 15:44:00 +0800 Date: Wed, 16 Jun 2021 15:44:01 +0800 From: Leo Liang To: CC: , Subject: [PULL] u-boot-riscv/next Message-ID: <20210616074401.GK6791@andestech.com> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline User-Agent: Mutt/1.5.24 (2015-08-30) X-Originating-IP: [10.0.15.65] X-DNSRBL: X-MAIL: ATCSQR.andestech.com 15G7i1AD034363 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean Hi Tom, Please pull u-boot-riscv/next into -next. The following changes on the "next" branch since commit c4737cd594b5c4c47aff789fc53f7dd36ed03c94: Merge tag 'xilinx-for-v2021.07-rc5' of https://source.denx.de/u-boot/custodians/u-boot-microblaze (2021-06-11 08:29:34 -0400) are available in the Git repository at: git@source.denx.de:u-boot/custodians/u-boot-riscv.git for you to fetch changes up to efbcd66af3c83b14efb72eb38f73cd4af8128208: test: Add K210 PLL tests to sandbox defconfigs (2021-06-16 10:04:23 +0800) CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/7856 ---------------------------------------------------------------- Bin Meng (6): riscv: ae350: dts: Add SPDX license header riscv: ae350: dts: Remove the unnecessary space in bootargs riscv: ae350: dts: Remove the unnecessary #address-cells in plic nodes riscv: ae350: dts: Fix #interrupt-cells for plic0 in 32-bit riscv: ae350: dts: Add missing "u-boot, dm-spl" for SPL config riscv: ae350: doc: Remove CONFIG_SKIP_LOWLEVEL_INIT Sean Anderson (11): clk: Allow force setting clock defaults before relocation clk: k210: Rewrite to remove CCF clk: k210: Move pll into the rest of the driver clk: k210: Implement soc_clk_dump clk: k210: Re-add support for setting rate clk: k210: Don't set PLL rates if we are already at the correct rate clk: k210: Remove bypass driver clk: k210: Move k210 clock out of its own subdirectory k210: dts: Set PLL1 to the same rate as PLL0 k210: Don't imply CCF test: Add K210 PLL tests to sandbox defconfigs MAINTAINERS | 4 +- arch/riscv/dts/ae350-u-boot.dtsi | 52 ++ arch/riscv/dts/ae350_32.dts | 9 +- arch/riscv/dts/ae350_64.dts | 7 +- arch/riscv/dts/k210.dtsi | 2 + board/sipeed/maix/Kconfig | 2 - configs/sandbox64_defconfig | 2 + configs/sandbox_defconfig | 2 + configs/sandbox_flattree_defconfig | 2 + configs/sipeed_maix_bitm_defconfig | 2 +- doc/board/AndesTech/ax25-ae350.rst | 19 +- drivers/clk/Kconfig | 14 +- drivers/clk/Makefile | 2 +- drivers/clk/clk-uclass.c | 27 +- drivers/clk/clk_kendryte.c | 1320 +++++++++++++++++++++++++++++++ drivers/clk/kendryte/Kconfig | 12 - drivers/clk/kendryte/Makefile | 1 - drivers/clk/kendryte/bypass.c | 273 ------- drivers/clk/kendryte/clk.c | 668 ---------------- drivers/clk/kendryte/pll.c | 585 -------------- drivers/clk/rockchip/clk_rk3308.c | 2 +- drivers/core/device.c | 2 +- drivers/net/gmac_rockchip.c | 2 +- include/clk.h | 30 +- include/dt-bindings/clock/k210-sysctl.h | 94 ++- include/kendryte/bypass.h | 31 - include/kendryte/clk.h | 35 - include/kendryte/pll.h | 34 - 28 files changed, 1502 insertions(+), 1733 deletions(-) create mode 100644 arch/riscv/dts/ae350-u-boot.dtsi create mode 100644 drivers/clk/clk_kendryte.c delete mode 100644 drivers/clk/kendryte/Kconfig delete mode 100644 drivers/clk/kendryte/Makefile delete mode 100644 drivers/clk/kendryte/bypass.c delete mode 100644 drivers/clk/kendryte/clk.c delete mode 100644 drivers/clk/kendryte/pll.c delete mode 100644 include/kendryte/bypass.h delete mode 100644 include/kendryte/clk.h Best regards, Leo