[PULL v2] u-boot-riscv/next

[Leo Liang <ycliang@andestech.com>]

Hi Tom,

Please pull u-boot-riscv/next into -next.

The following changes on the "next" branch since commit c4737cd594b5c4c47aff789fc53f7dd36ed03c94:

  Merge tag 'xilinx-for-v2021.07-rc5' of https://source.denx.de/u-boot/custodians/u-boot-microblaze (2021-06-11 08:29:34 -0400)

are available in the Git repository at:

  git@source.denx.de:u-boot/custodians/u-boot-riscv.git 

for you to fetch changes up to d1d256e1635684615182aaf62b077233c3360f7e:

  riscv: andes_plic: Fix riscv_get_ipi() mask (2021-06-16 16:20:13 +0800)

CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/7857

----------------------------------------------------------------
Bin Meng (7):
      riscv: ae350: dts: Add SPDX license header
      riscv: ae350: dts: Remove the unnecessary space in bootargs
      riscv: ae350: dts: Remove the unnecessary #address-cells in plic nodes
      riscv: ae350: dts: Fix #interrupt-cells for plic0 in 32-bit
      riscv: ae350: dts: Add missing "u-boot, dm-spl" for SPL config
      riscv: ae350: doc: Remove CONFIG_SKIP_LOWLEVEL_INIT
      riscv: andes_plic: Fix riscv_get_ipi() mask

Sean Anderson (11):
      clk: Allow force setting clock defaults before relocation
      clk: k210: Rewrite to remove CCF
      clk: k210: Move pll into the rest of the driver
      clk: k210: Implement soc_clk_dump
      clk: k210: Re-add support for setting rate
      clk: k210: Don't set PLL rates if we are already at the correct rate
      clk: k210: Remove bypass driver
      clk: k210: Move k210 clock out of its own subdirectory
      k210: dts: Set PLL1 to the same rate as PLL0
      k210: Don't imply CCF
      test: Add K210 PLL tests to sandbox defconfigs

 MAINTAINERS                             |    4 +-
 arch/riscv/dts/ae350-u-boot.dtsi        |   52 ++
 arch/riscv/dts/ae350_32.dts             |    9 +-
 arch/riscv/dts/ae350_64.dts             |    7 +-
 arch/riscv/dts/k210.dtsi                |    2 +
 arch/riscv/lib/andes_plic.c             |    4 +-
 board/sipeed/maix/Kconfig               |    2 -
 configs/sandbox64_defconfig             |    2 +
 configs/sandbox_defconfig               |    2 +
 configs/sandbox_flattree_defconfig      |    2 +
 configs/sipeed_maix_bitm_defconfig      |    2 +-
 doc/board/AndesTech/ax25-ae350.rst      |   19 +-
 drivers/clk/Kconfig                     |   14 +-
 drivers/clk/Makefile                    |    2 +-
 drivers/clk/clk-uclass.c                |   27 +-
 drivers/clk/clk_kendryte.c              | 1320 +++++++++++++++++++++++++++++++
 drivers/clk/kendryte/Kconfig            |   12 -
 drivers/clk/kendryte/Makefile           |    1 -
 drivers/clk/kendryte/bypass.c           |  273 -------
 drivers/clk/kendryte/clk.c              |  668 ----------------
 drivers/clk/kendryte/pll.c              |  585 --------------
 drivers/clk/rockchip/clk_rk3308.c       |    2 +-
 drivers/core/device.c                   |    2 +-
 drivers/net/gmac_rockchip.c             |    2 +-
 include/clk.h                           |   30 +-
 include/dt-bindings/clock/k210-sysctl.h |   94 ++-
 include/kendryte/bypass.h               |   31 -
 include/kendryte/clk.h                  |   35 -
 include/kendryte/pll.h                  |   34 -
 29 files changed, 1505 insertions(+), 1734 deletions(-)
 create mode 100644 arch/riscv/dts/ae350-u-boot.dtsi
 create mode 100644 drivers/clk/clk_kendryte.c
 delete mode 100644 drivers/clk/kendryte/Kconfig
 delete mode 100644 drivers/clk/kendryte/Makefile
 delete mode 100644 drivers/clk/kendryte/bypass.c
 delete mode 100644 drivers/clk/kendryte/clk.c
 delete mode 100644 drivers/clk/kendryte/pll.c
 delete mode 100644 include/kendryte/bypass.h
 delete mode 100644 include/kendryte/clk.h

 Best regards,
 Leo