From: Johan Jonker <jbx6244@gmail.com>
To: kever.yang@rock-chips.com
Cc: sjg@chromium.org, philipp.tomsich@vrull.eu, heiko@sntech.de,
paweljarosz3691@gmail.com, u-boot@lists.denx.de
Subject: [PATCH v1] rockchip: rk3188-cru-common: sync clock dt-binding header from Linux
Date: Mon, 21 Jun 2021 09:39:20 +0200 [thread overview]
Message-ID: <20210621073920.2675-1-jbx6244@gmail.com> (raw)
In order to update the DT for rk3066 and rk3188
sync the clock dt-binding header.
This is the state as of v5.12 in Linux.
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
---
include/dt-bindings/clock/rk3188-cru-common.h | 12 +++++++++---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/include/dt-bindings/clock/rk3188-cru-common.h b/include/dt-bindings/clock/rk3188-cru-common.h
index 1e7931da0c..afad90680f 100644
--- a/include/dt-bindings/clock/rk3188-cru-common.h
+++ b/include/dt-bindings/clock/rk3188-cru-common.h
@@ -1,4 +1,4 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
+/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright (c) 2014 MundoReader S.L.
* Author: Heiko Stuebner <heiko@sntech.de>
@@ -59,12 +59,14 @@
#define ACLK_LCDC1 196
#define ACLK_GPU 197
#define ACLK_SMC 198
-#define ACLK_CIF 199
+#define ACLK_CIF1 199
#define ACLK_IPP 200
#define ACLK_RGA 201
#define ACLK_CIF0 202
#define ACLK_CPU 203
#define ACLK_PERI 204
+#define ACLK_VEPU 205
+#define ACLK_VDPU 206
/* pclk gates */
#define PCLK_GRF 320
@@ -125,8 +127,12 @@
#define HCLK_NANDC0 467
#define HCLK_CPU 468
#define HCLK_PERI 469
+#define HCLK_CIF1 470
+#define HCLK_VEPU 471
+#define HCLK_VDPU 472
+#define HCLK_HDMI 473
-#define CLK_NR_CLKS (HCLK_PERI + 1)
+#define CLK_NR_CLKS (HCLK_HDMI + 1)
/* soft-reset indices */
#define SRST_MCORE 2
--
2.11.0
next reply other threads:[~2021-06-21 16:54 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-06-21 7:39 Johan Jonker [this message]
2021-06-21 9:02 ` [PATCH v1] rockchip: rk3188-cru-common: sync clock dt-binding header from Linux Heiko Stübner
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