From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.3 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9B415C11F65 for ; Wed, 30 Jun 2021 07:14:39 +0000 (UTC) Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id BF49F61CC1 for ; Wed, 30 Jun 2021 07:14:38 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org BF49F61CC1 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=andestech.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id BDF778324A; Wed, 30 Jun 2021 09:14:36 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=andestech.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id 6701083246; Wed, 30 Jun 2021 09:14:34 +0200 (CEST) Received: from ATCSQR.andestech.com (exmail.andestech.com [60.248.187.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 8393883246 for ; Wed, 30 Jun 2021 09:14:30 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=andestech.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=ycliang@andestech.com Received: from mail.andestech.com (atcpcs16.andestech.com [10.0.1.222]) by ATCSQR.andestech.com with ESMTP id 15U7EOBi086099; Wed, 30 Jun 2021 15:14:24 +0800 (GMT-8) (envelope-from ycliang@andestech.com) Received: from andestech.com (10.0.15.65) by ATCPCS16.andestech.com (10.0.1.222) with Microsoft SMTP Server id 14.3.498.0; Wed, 30 Jun 2021 15:14:25 +0800 Date: Wed, 30 Jun 2021 15:14:23 +0800 From: Leo Liang To: Tianrui Wei CC: Subject: Re: [PATCH v8 1/2] board: riscv: add openpiton-riscv64 SoC support Message-ID: <20210630071423.GA29132@andestech.com> References: <20210630015155.15703-1-tianrui-wei@outlook.com> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.24 (2015-08-30) X-Originating-IP: [10.0.15.65] X-DNSRBL: X-MAIL: ATCSQR.andestech.com 15U7EOBi086099 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean Hi Tianrui, On Wed, Jun 30, 2021 at 09:51:54AM +0800, Tianrui Wei wrote: > This patch adds openpiton-riscv64 SOC support. In particular, this > board supports a standard bootflow through zsbl->u-boot SPL-> > opensbi->u-boot proper->Linux. There are separate defconfigs for > building u-boot SPL and u-boot proper > > - V6 > . separate defconfigs for u-boot and SPL > . eliminate debug console output > . style updates > - V7 > . update Kconfig for OpenPiton board > . SPL defconfig updates > > Signed-off-by: Tianrui Wei > Signed-off-by: Jonathan Balkind > --- > arch/riscv/Kconfig | 4 + > arch/riscv/dts/Makefile | 1 + > arch/riscv/dts/openpiton-riscv64.dts | 153 ++++++++ > board/openpiton/riscv64/Kconfig | 40 +++ > board/openpiton/riscv64/MAINTAINERS | 8 + > board/openpiton/riscv64/Makefile | 5 + > board/openpiton/riscv64/openpiton-riscv64.c | 33 ++ > configs/openpiton_riscv64_defconfig | 76 ++++ > configs/openpiton_riscv64_spl_defconfig | 87 +++++ > doc/board/index.rst | 1 + > doc/board/openpiton/index.rst | 9 + > doc/board/openpiton/riscv64.rst | 376 ++++++++++++++++++++ > include/configs/openpiton-riscv64.h | 61 ++++ > 13 files changed, 854 insertions(+) > create mode 100644 arch/riscv/dts/openpiton-riscv64.dts > create mode 100644 board/openpiton/riscv64/Kconfig > create mode 100644 board/openpiton/riscv64/MAINTAINERS > create mode 100644 board/openpiton/riscv64/Makefile > create mode 100644 board/openpiton/riscv64/openpiton-riscv64.c > create mode 100644 configs/openpiton_riscv64_defconfig > create mode 100644 configs/openpiton_riscv64_spl_defconfig > create mode 100644 doc/board/openpiton/index.rst > create mode 100644 doc/board/openpiton/riscv64.rst > create mode 100644 include/configs/openpiton-riscv64.h > > diff --git a/doc/board/openpiton/riscv64.rst b/doc/board/openpiton/riscv64.rst > new file mode 100644 > index 0000000000..ed7d59db2c > --- /dev/null > +++ b/doc/board/openpiton/riscv64.rst > @@ -0,0 +1,376 @@ > +.. SPDX-License-Identifier: GPL-2.0+ > + > +Openpiton RISC-V SoC > +==================== > + > +OpenPiton RISC-V SoC > +-------------------- > +OpenPiton is an open source, manycore processor and research platform. It is a > +tiled manycore framework scalable from one to 1/2 billion cores. It supports a > +number of ISAs including RISC-V with its P-Mesh cache coherence protocol and > +networks on chip. It is highly configurable in both core and uncore components. > +OpenPiton has been verified in both ASIC and multiple Xilinx FPGA prototypes > +running full-stack Debian linux. > + > +RISCV-V Standard Bootflow typo: RISC-V Otherwise, LGTM. Best regards, Leo > +------------------------- > +Currently, OpenPiton implements RISC-V standard bootflow in the following steps > +mover.S -> u-boot-spl -> opensbi -> u-boot -> Linux > +This board supports S-mode u-boot as well as M-mode SPL