From: Leo Liang <ycliang@andestech.com>
To: Tianrui Wei <tianrui-wei@outlook.com>
Cc: <u-boot@lists.denx.de>
Subject: Re: [PATCH v8 1/2] board: riscv: add openpiton-riscv64 SoC support
Date: Wed, 30 Jun 2021 15:26:35 +0800 [thread overview]
Message-ID: <20210630072635.GA18251@andestech.com> (raw)
In-Reply-To: <20210630071423.GA29132@andestech.com>
Hi Tianrui,
On Wed, Jun 30, 2021 at 03:14:23PM +0800, Leo Liang wrote:
> Hi Tianrui,
> On Wed, Jun 30, 2021 at 09:51:54AM +0800, Tianrui Wei wrote:
> > This patch adds openpiton-riscv64 SOC support. In particular, this
> > board supports a standard bootflow through zsbl->u-boot SPL->
> > opensbi->u-boot proper->Linux. There are separate defconfigs for
> > building u-boot SPL and u-boot proper
> >
> > - V6
> > . separate defconfigs for u-boot and SPL
> > . eliminate debug console output
> > . style updates
> > - V7
> > . update Kconfig for OpenPiton board
> > . SPL defconfig updates
Sorry,
forgot to mention these change logs should only be present in the cover letter.
Best regards,
Leo
> >
> > Signed-off-by: Tianrui Wei <tianrui-wei@outlook.com>
> > Signed-off-by: Jonathan Balkind <jbalkind@ucsb.edu>
> > ---
> > arch/riscv/Kconfig | 4 +
> > arch/riscv/dts/Makefile | 1 +
> > arch/riscv/dts/openpiton-riscv64.dts | 153 ++++++++
> > board/openpiton/riscv64/Kconfig | 40 +++
> > board/openpiton/riscv64/MAINTAINERS | 8 +
> > board/openpiton/riscv64/Makefile | 5 +
> > board/openpiton/riscv64/openpiton-riscv64.c | 33 ++
> > configs/openpiton_riscv64_defconfig | 76 ++++
> > configs/openpiton_riscv64_spl_defconfig | 87 +++++
> > doc/board/index.rst | 1 +
> > doc/board/openpiton/index.rst | 9 +
> > doc/board/openpiton/riscv64.rst | 376 ++++++++++++++++++++
> > include/configs/openpiton-riscv64.h | 61 ++++
> > 13 files changed, 854 insertions(+)
> > create mode 100644 arch/riscv/dts/openpiton-riscv64.dts
> > create mode 100644 board/openpiton/riscv64/Kconfig
> > create mode 100644 board/openpiton/riscv64/MAINTAINERS
> > create mode 100644 board/openpiton/riscv64/Makefile
> > create mode 100644 board/openpiton/riscv64/openpiton-riscv64.c
> > create mode 100644 configs/openpiton_riscv64_defconfig
> > create mode 100644 configs/openpiton_riscv64_spl_defconfig
> > create mode 100644 doc/board/openpiton/index.rst
> > create mode 100644 doc/board/openpiton/riscv64.rst
> > create mode 100644 include/configs/openpiton-riscv64.h
> >
> > diff --git a/doc/board/openpiton/riscv64.rst b/doc/board/openpiton/riscv64.rst
> > new file mode 100644
> > index 0000000000..ed7d59db2c
> > --- /dev/null
> > +++ b/doc/board/openpiton/riscv64.rst
> > @@ -0,0 +1,376 @@
> > +.. SPDX-License-Identifier: GPL-2.0+
> > +
> > +Openpiton RISC-V SoC
> > +====================
> > +
> > +OpenPiton RISC-V SoC
> > +--------------------
> > +OpenPiton is an open source, manycore processor and research platform. It is a
> > +tiled manycore framework scalable from one to 1/2 billion cores. It supports a
> > +number of ISAs including RISC-V with its P-Mesh cache coherence protocol and
> > +networks on chip. It is highly configurable in both core and uncore components.
> > +OpenPiton has been verified in both ASIC and multiple Xilinx FPGA prototypes
> > +running full-stack Debian linux.
> > +
> > +RISCV-V Standard Bootflow
>
> typo: RISC-V
>
> Otherwise, LGTM.
> Best regards,
> Leo
>
> > +-------------------------
> > +Currently, OpenPiton implements RISC-V standard bootflow in the following steps
> > +mover.S -> u-boot-spl -> opensbi -> u-boot -> Linux
> > +This board supports S-mode u-boot as well as M-mode SPL
next prev parent reply other threads:[~2021-06-30 7:27 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <20210630015155.15703-1-tianrui-wei@outlook.com>
2021-06-30 1:51 ` [PATCH v8 1/2] board: riscv: add openpiton-riscv64 SoC support Tianrui Wei
2021-06-30 7:14 ` Leo Liang
2021-06-30 7:26 ` Leo Liang [this message]
2021-06-30 1:51 ` [PATCH v8 2/2] mmc: openpiton: add piton_mmc driver Tianrui Wei
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