From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-10.2 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_SANE_2 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 50F32C07E96 for ; Tue, 6 Jul 2021 16:00:44 +0000 (UTC) Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 2187E61879 for ; Tue, 6 Jul 2021 16:00:43 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 2187E61879 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=bootlin.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id DD74482D88; Tue, 6 Jul 2021 18:00:40 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=bootlin.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id 2D51C82D8A; Tue, 6 Jul 2021 18:00:39 +0200 (CEST) Received: from relay11.mail.gandi.net (relay11.mail.gandi.net [217.70.178.231]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 1F03682C81 for ; Tue, 6 Jul 2021 18:00:36 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=bootlin.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=miquel.raynal@bootlin.com Received: (Authenticated sender: miquel.raynal@bootlin.com) by relay11.mail.gandi.net (Postfix) with ESMTPSA id E8F2C100006; Tue, 6 Jul 2021 16:00:34 +0000 (UTC) Date: Tue, 6 Jul 2021 18:00:33 +0200 From: Miquel Raynal To: Maxime Ripard Cc: u-boot@lists.denx.de, Andre Przywara Subject: Re: [U-Boot] [PATCH v3 13/20] spl: nand: sunxi: use PIO instead of DMA Message-ID: <20210706180033.00a81eb0@xps13> In-Reply-To: <20210624120540.7oyhdmerjndsylbq@gilmour> References: <20180228195202.8183-1-miquel.raynal@bootlin.com> <20180228195202.8183-14-miquel.raynal@bootlin.com> <20210624120540.7oyhdmerjndsylbq@gilmour> Organization: Bootlin X-Mailer: Claws Mail 3.17.7 (GTK+ 2.24.32; x86_64-pc-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean Hi Maxime, Maxime Ripard wrote on Thu, 24 Jun 2021 14:05:40 +0200: > Hi Miquel, >=20 > On Wed, Feb 28, 2018 at 08:51:55PM +0100, Miquel Raynal wrote: > > SPL support was first written to support only the earlier generations of > > Allwinner SoCs, and was only really enabled on the A13 / GR8. However, > > those old SoCs had a DMA engine that has been replaced since the A31 by > > another DMA controller that is no longer compatible. > >=20 > > Since the code directly uses that DMA controller, it cannot operate > > properly on the later SoCs, while the NAND controller has not changed. > >=20 > > There's two paths forward, the first one would have been to add support > > for that DMA controller too, the second to just remove the DMA usage > > entirely and rely on PIO. > >=20 > > The later has been chosen because CPU overload at this stage is not an > > issue and it makes the driver more generic, and easier to understand. > >=20 > > Signed-off-by: Miquel Raynal > > Acked-by: Boris Brezillon =20 >=20 > I'm a bit late to the party, but this bricks the CHIP Pro too. While > U-Boot proper seems to be flashed properly (re-reading it from the NAND > after flashing brings up the same CRC than the original image), the SPL > will only read 0s. >=20 > The transfer does complete though, so maybe it's just the copy from the > SRAM to the main memory that doesn't work? >=20 > The offset looks correct though, so I'm not sure. Strange... I really have no idea what's going on here and especially I don't have any suitable board with me these days to troubleshoot this. Sorry for not being helpful at all on this one :-) Thanks, Miqu=C3=A8l