From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.5 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_SANE_2 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id AD98AC07E9C for ; Sat, 10 Jul 2021 23:52:40 +0000 (UTC) Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id B23AA6141C for ; Sat, 10 Jul 2021 23:52:39 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org B23AA6141C Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id BBADE82C7A; Sun, 11 Jul 2021 01:52:37 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id 91A9D82C7B; Sun, 11 Jul 2021 01:52:35 +0200 (CEST) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by phobos.denx.de (Postfix) with ESMTP id BD41C82C6E for ; Sun, 11 Jul 2021 01:52:32 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=andre.przywara@arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id C4DEC1063; Sat, 10 Jul 2021 16:52:31 -0700 (PDT) Received: from slackpad.fritz.box (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 01D173F66F; Sat, 10 Jul 2021 16:52:30 -0700 (PDT) Date: Sun, 11 Jul 2021 00:51:55 +0100 From: Andre Przywara To: Samuel Holland Cc: Jagan Teki , Hans de Goede , u-boot@lists.denx.de Subject: Re: [PATCH] sunxi: Load sun8i secure monitor to SRAM A2 Message-ID: <20210711005155.766dad98@slackpad.fritz.box> In-Reply-To: <20210419032141.33620-1-samuel@sholland.org> References: <20210419032141.33620-1-samuel@sholland.org> Organization: Arm Ltd. X-Mailer: Claws Mail 3.17.1 (GTK+ 2.24.31; x86_64-slackware-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean On Sun, 18 Apr 2021 22:21:41 -0500 Samuel Holland wrote: Hi Samuel, > Most sun6i-derived SoCs contain SRAM A2, a secure SRAM area for ARISC > SCP firmware. H3 has a smaller SRAM than other SoCs (A31/A33/A23/A83T). > > On sun8i SoCs which do not have SRAM B, we can use part of this SRAM for > the secure monitor. Follow the design of 64-bit SoCs and use the first > part for the monitor, and the last 16 KiB for the SCP firmware. With > this change, the monitor no longer needs to reserve a region in DRAM. So this commit message reads a bit more innocent than the patch is, can you amend this? It took me a while to see what it really does ... For a start, I'd suggest to rename the subject to "Move secure monitor...". And it's good to explain where we come from (SRAM B vs. SRAM A2), but I would like to see an explicit list of SoCs that get changed, because all those different sun8i.h, cpu_sun4i.h and CONFIG_SUN8I parts are super confusing to the casual reader. Maybe something along the lines of: So far for the H3, A23, and A33 SoCs, we use DRAM to hold the secure monitor. And while those SoCs do not have the secure SRAM B like older SoCs, there is enough (secure) SRAM A2 to put the monitor code and data in there instead .... Regardless of that, the patch is nice, I always disliked reserving a small piece of DRAM somewhere in the middle of it. If I see this correctly, this just leaves the R40 using DRAM for the secure monitor (with V3s and A83T not using PSCI)? Cheers, Andre > > Signed-off-by: Samuel Holland > --- > arch/arm/include/asm/arch-sunxi/cpu_sun4i.h | 11 +++++++++++ > include/configs/sun8i.h | 7 +++++++ > 2 files changed, 18 insertions(+) > > diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h > index 02ce73954d..d4c795d89c 100644 > --- a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h > +++ b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h > @@ -11,7 +11,18 @@ > #define SUNXI_SRAM_A1_BASE 0x00000000 > #define SUNXI_SRAM_A1_SIZE (16 * 1024) /* 16 kiB */ > > +#if defined(CONFIG_SUNXI_GEN_SUN6I) && \ > + !defined(CONFIG_MACH_SUN8I_R40) && \ > + !defined(CONFIG_MACH_SUN8I_V3S) > +#define SUNXI_SRAM_A2_BASE 0x00040000 > +#ifdef CONFIG_MACH_SUN8I_H3 > +#define SUNXI_SRAM_A2_SIZE (48 * 1024) /* 16+32 kiB */ > +#else > +#define SUNXI_SRAM_A2_SIZE (80 * 1024) /* 16+64 kiB */ > +#endif > +#else > #define SUNXI_SRAM_A2_BASE 0x00004000 /* 16 kiB */ > +#endif > #define SUNXI_SRAM_A3_BASE 0x00008000 /* 13 kiB */ > #define SUNXI_SRAM_A4_BASE 0x0000b400 /* 3 kiB */ > #define SUNXI_SRAM_D_BASE 0x00010000 /* 4 kiB */ > diff --git a/include/configs/sun8i.h b/include/configs/sun8i.h > index 9b4675e4c3..545d27996c 100644 > --- a/include/configs/sun8i.h > +++ b/include/configs/sun8i.h > @@ -12,6 +12,13 @@ > * A23 specific configuration > */ > > +/* > + * Skip the first 16 KiB of SRAM A2, which is not usable, as only certain bytes > + * are writable. Reserve the last 17 KiB for the resume shim and SCP firmware. > + */ > +#define CONFIG_ARMV7_SECURE_BASE (SUNXI_SRAM_A2_BASE + 16 * 1024) > +#define CONFIG_ARMV7_SECURE_MAX_SIZE (SUNXI_SRAM_A2_SIZE - 33 * 1024) > + > /* > * Include common sunxi configuration where most the settings are > */