* [PATCH v1 1/1] x86: tangier: Fix DMA controller IRQ polarity in CSRT
@ 2021-07-30 20:15 Andy Shevchenko
2021-07-30 23:44 ` Bin Meng
2021-07-31 1:03 ` Simon Glass
0 siblings, 2 replies; 5+ messages in thread
From: Andy Shevchenko @ 2021-07-30 20:15 UTC (permalink / raw)
To: Andy Shevchenko, u-boot; +Cc: Simon Glass, Bin Meng
IRQ polarity in CSRT has the same definition as by ACPI specification
chapter 19.6.64 "Interrupt (Interrupt Resource Descriptor Macro)", i.e.
ActiveHigh is 0, and ActiveLow is 1. On Intel Tangier the DMA controller
IRQ polarity is ActiveHigh.
Note, in DSDT (see southcluster.asl) it's described correctly.
Fixes: 5e99fde34a77 ("x86: tangier: Populate CSRT for shared DMA controller")
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
---
arch/x86/cpu/tangier/acpi.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/x86/cpu/tangier/acpi.c b/arch/x86/cpu/tangier/acpi.c
index 41bd177e095f..82f4ce5a34a4 100644
--- a/arch/x86/cpu/tangier/acpi.c
+++ b/arch/x86/cpu/tangier/acpi.c
@@ -89,8 +89,8 @@ static u32 acpi_fill_csrt_dma(struct acpi_csrt_group *grp)
si->mmio_base_low = 0xff192000;
si->mmio_base_high = 0;
si->gsi_interrupt = 32;
- si->interrupt_polarity = 1;
- si->interrupt_mode = 0;
+ si->interrupt_polarity = 0; /* Active High */
+ si->interrupt_mode = 0; /* Level triggered */
si->num_channels = 8;
si->dma_address_width = 32;
si->base_request_line = 0;
--
2.30.2
^ permalink raw reply related [flat|nested] 5+ messages in thread* Re: [PATCH v1 1/1] x86: tangier: Fix DMA controller IRQ polarity in CSRT
2021-07-30 20:15 [PATCH v1 1/1] x86: tangier: Fix DMA controller IRQ polarity in CSRT Andy Shevchenko
@ 2021-07-30 23:44 ` Bin Meng
2021-07-31 1:02 ` Bin Meng
2021-07-31 1:03 ` Simon Glass
1 sibling, 1 reply; 5+ messages in thread
From: Bin Meng @ 2021-07-30 23:44 UTC (permalink / raw)
To: Andy Shevchenko; +Cc: U-Boot Mailing List, Simon Glass
On Sat, Jul 31, 2021 at 4:15 AM Andy Shevchenko
<andriy.shevchenko@linux.intel.com> wrote:
>
> IRQ polarity in CSRT has the same definition as by ACPI specification
> chapter 19.6.64 "Interrupt (Interrupt Resource Descriptor Macro)", i.e.
> ActiveHigh is 0, and ActiveLow is 1. On Intel Tangier the DMA controller
> IRQ polarity is ActiveHigh.
>
> Note, in DSDT (see southcluster.asl) it's described correctly.
>
> Fixes: 5e99fde34a77 ("x86: tangier: Populate CSRT for shared DMA controller")
> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> ---
> arch/x86/cpu/tangier/acpi.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
^ permalink raw reply [flat|nested] 5+ messages in thread* Re: [PATCH v1 1/1] x86: tangier: Fix DMA controller IRQ polarity in CSRT
2021-07-30 23:44 ` Bin Meng
@ 2021-07-31 1:02 ` Bin Meng
0 siblings, 0 replies; 5+ messages in thread
From: Bin Meng @ 2021-07-31 1:02 UTC (permalink / raw)
To: Andy Shevchenko; +Cc: U-Boot Mailing List, Simon Glass
On Sat, Jul 31, 2021 at 7:44 AM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> On Sat, Jul 31, 2021 at 4:15 AM Andy Shevchenko
> <andriy.shevchenko@linux.intel.com> wrote:
> >
> > IRQ polarity in CSRT has the same definition as by ACPI specification
> > chapter 19.6.64 "Interrupt (Interrupt Resource Descriptor Macro)", i.e.
> > ActiveHigh is 0, and ActiveLow is 1. On Intel Tangier the DMA controller
> > IRQ polarity is ActiveHigh.
> >
> > Note, in DSDT (see southcluster.asl) it's described correctly.
> >
> > Fixes: 5e99fde34a77 ("x86: tangier: Populate CSRT for shared DMA controller")
> > Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> > ---
> > arch/x86/cpu/tangier/acpi.c | 4 ++--
> > 1 file changed, 2 insertions(+), 2 deletions(-)
> >
>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
applied to u-boot-x86, thanks!
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH v1 1/1] x86: tangier: Fix DMA controller IRQ polarity in CSRT
2021-07-30 20:15 [PATCH v1 1/1] x86: tangier: Fix DMA controller IRQ polarity in CSRT Andy Shevchenko
2021-07-30 23:44 ` Bin Meng
@ 2021-07-31 1:03 ` Simon Glass
2021-07-31 1:06 ` Bin Meng
1 sibling, 1 reply; 5+ messages in thread
From: Simon Glass @ 2021-07-31 1:03 UTC (permalink / raw)
To: Andy Shevchenko; +Cc: U-Boot Mailing List, Bin Meng
On Fri, 30 Jul 2021 at 14:15, Andy Shevchenko
<andriy.shevchenko@linux.intel.com> wrote:
>
> IRQ polarity in CSRT has the same definition as by ACPI specification
> chapter 19.6.64 "Interrupt (Interrupt Resource Descriptor Macro)", i.e.
> ActiveHigh is 0, and ActiveLow is 1. On Intel Tangier the DMA controller
> IRQ polarity is ActiveHigh.
>
> Note, in DSDT (see southcluster.asl) it's described correctly.
>
> Fixes: 5e99fde34a77 ("x86: tangier: Populate CSRT for shared DMA controller")
> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> ---
> arch/x86/cpu/tangier/acpi.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
Reviewed-by: Simon Glass <sjg@chromium.org>
^ permalink raw reply [flat|nested] 5+ messages in thread* Re: [PATCH v1 1/1] x86: tangier: Fix DMA controller IRQ polarity in CSRT
2021-07-31 1:03 ` Simon Glass
@ 2021-07-31 1:06 ` Bin Meng
0 siblings, 0 replies; 5+ messages in thread
From: Bin Meng @ 2021-07-31 1:06 UTC (permalink / raw)
To: Simon Glass; +Cc: Andy Shevchenko, U-Boot Mailing List
Hi Simon,
On Sat, Jul 31, 2021 at 9:03 AM Simon Glass <sjg@chromium.org> wrote:
>
> On Fri, 30 Jul 2021 at 14:15, Andy Shevchenko
> <andriy.shevchenko@linux.intel.com> wrote:
> >
> > IRQ polarity in CSRT has the same definition as by ACPI specification
> > chapter 19.6.64 "Interrupt (Interrupt Resource Descriptor Macro)", i.e.
> > ActiveHigh is 0, and ActiveLow is 1. On Intel Tangier the DMA controller
> > IRQ polarity is ActiveHigh.
> >
> > Note, in DSDT (see southcluster.asl) it's described correctly.
> >
> > Fixes: 5e99fde34a77 ("x86: tangier: Populate CSRT for shared DMA controller")
> > Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> > ---
> > arch/x86/cpu/tangier/acpi.c | 4 ++--
> > 1 file changed, 2 insertions(+), 2 deletions(-)
>
> Reviewed-by: Simon Glass <sjg@chromium.org>
Oops, this was applied 1 minute earlier :-)
I've added your RB tag manually.
Regards,
Bin
^ permalink raw reply [flat|nested] 5+ messages in thread
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2021-07-30 20:15 [PATCH v1 1/1] x86: tangier: Fix DMA controller IRQ polarity in CSRT Andy Shevchenko
2021-07-30 23:44 ` Bin Meng
2021-07-31 1:02 ` Bin Meng
2021-07-31 1:03 ` Simon Glass
2021-07-31 1:06 ` Bin Meng
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