From: Bin Meng <bmeng.cn@gmail.com>
To: u-boot@lists.denx.de, Simon Glass <sjg@chromium.org>
Subject: [PATCH v3 0/2] x86: Various fixes to MTRR and FSP codes
Date: Mon, 2 Aug 2021 17:45:20 +0800 [thread overview]
Message-ID: <20210802094522.761676-1-bmeng.cn@gmail.com> (raw)
At present Intel Crown Bay does not boot. This was caused by various
regression issues introduced when supporting FSP2, and some flaws in
MTRR codes.
With this series, U-Boot boot again on Intel Crown Bay board.
Changes in v3:
- Add the missing header file include
Changes in v2:
- Keep programing MTRR to FSP2 only
- Move board_final_cleanup() to fsp2 directory
Bin Meng (2):
x86: fsp: Don't program MTRR for DRAM for FSP1
x86: fsp: Only FSP2 has INIT_PHASE_END_FIRMWARE
arch/x86/lib/fsp/fsp_common.c | 16 ----------------
arch/x86/lib/fsp/fsp_dram.c | 27 +++++++++++++++++++++++----
arch/x86/lib/fsp2/fsp_common.c | 17 +++++++++++++++++
3 files changed, 40 insertions(+), 20 deletions(-)
--
2.25.1
next reply other threads:[~2021-08-02 9:45 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-08-02 9:45 Bin Meng [this message]
2021-08-02 9:45 ` [PATCH v3 1/2] x86: fsp: Don't program MTRR for DRAM for FSP1 Bin Meng
2021-08-02 14:44 ` Simon Glass
2021-08-02 16:00 ` Bin Meng
2021-08-02 9:45 ` [PATCH v3 2/2] x86: fsp: Only FSP2 has INIT_PHASE_END_FIRMWARE Bin Meng
2021-08-02 14:44 ` Simon Glass
2021-08-02 16:00 ` Bin Meng
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