[PATCH 0/2] rockchip: board: Fix bug for clk driver for OGA

[PATCH 0/2] rockchip: board: Fix bug for clk driver for OGA

[Chris Morgan]

From: Chris Morgan <macromorgan@hotmail.com>

This series is to fix a problem with probing the clk_px30 driver that
began with commit 92f1e9a4b31c ("clk: Detect failure to set defaults").
The driver fails to probe because 2 clocks are unsupported. One clock
(the cpll) was simple to add to the driver and the other clock (the
GPU) is not used in U-Boot so was removed from the U-Boot specific
device tree. With these changes the clk driver probes again
successfully. Note that without this fix no devices that depend on the
clk driver are able to probe as well (such as the SD card, the SPI
bus, etc) so the device fails to boot.

Chris Morgan (2):
  rockchip: px30: add support for setting cpll clock
  rockchip: board: remove SCLK_GPU from U-Boot DT

 arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi | 10 ++++++++++
 drivers/clk/rockchip/clk_px30.c            |  3 +++
 2 files changed, 13 insertions(+)

-- 
2.25.1

[PATCH 1/2] rockchip: px30: add support for setting cpll clock

[Chris Morgan]

From: Chris Morgan <macromorgan@hotmail.com>

Starting with commit 92f1e9a4b31c ("clk: Detect failure to set
defaults") the clk driver for the PX30 for the Odroid Go Advance would
no longer probe correctly, because setting the cpll and gpu clocks are
not supported with the clk_px30 U-Boot driver. This adds support for
setting the cpll clock to the clk_px30 driver. Another patch will
update the U-Boot specific device-tree to remove the GPU clock which is
not used by U-Boot.

Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
---
 drivers/clk/rockchip/clk_px30.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/clk/rockchip/clk_px30.c b/drivers/clk/rockchip/clk_px30.c
index 6b746f4c65..89784f9aa1 100644
--- a/drivers/clk/rockchip/clk_px30.c
+++ b/drivers/clk/rockchip/clk_px30.c
@@ -1262,6 +1262,9 @@ static ulong px30_clk_set_rate(struct clk *clk, ulong rate)
 	case PLL_NPLL:
 		ret = px30_clk_set_pll_rate(priv, NPLL, rate);
 		break;
+	case PLL_CPLL:
+		ret = px30_clk_set_pll_rate(priv, CPLL, rate);
+		break;
 	case ARMCLK:
 		ret = px30_armclk_set_clk(priv, rate);
 		break;
-- 
2.25.1

Re: [PATCH 1/2] rockchip: px30: add support for setting cpll clock

[Kever Yang]

Reviewed-by: Kever Yang <kever.yang@rock-chips.com>


Thanks,
- Kever

Chris Morgan <macroalpha82@gmail.com> 于2021年8月6日周五 上午12:49写道：
>
> From: Chris Morgan <macromorgan@hotmail.com>
>
> Starting with commit 92f1e9a4b31c ("clk: Detect failure to set
> defaults") the clk driver for the PX30 for the Odroid Go Advance would
> no longer probe correctly, because setting the cpll and gpu clocks are
> not supported with the clk_px30 U-Boot driver. This adds support for
> setting the cpll clock to the clk_px30 driver. Another patch will
> update the U-Boot specific device-tree to remove the GPU clock which is
> not used by U-Boot.
>
> Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
> ---
>  drivers/clk/rockchip/clk_px30.c | 3 +++
>  1 file changed, 3 insertions(+)
>
> diff --git a/drivers/clk/rockchip/clk_px30.c b/drivers/clk/rockchip/clk_px30.c
> index 6b746f4c65..89784f9aa1 100644
> --- a/drivers/clk/rockchip/clk_px30.c
> +++ b/drivers/clk/rockchip/clk_px30.c
> @@ -1262,6 +1262,9 @@ static ulong px30_clk_set_rate(struct clk *clk, ulong rate)
>         case PLL_NPLL:
>                 ret = px30_clk_set_pll_rate(priv, NPLL, rate);
>                 break;
> +       case PLL_CPLL:
> +               ret = px30_clk_set_pll_rate(priv, CPLL, rate);
> +               break;
>         case ARMCLK:
>                 ret = px30_armclk_set_clk(priv, rate);
>                 break;
> --
> 2.25.1
>

[PATCH 2/2] rockchip: board: remove SCLK_GPU from U-Boot DT

[Chris Morgan]

From: Chris Morgan <macromorgan@hotmail.com>

Starting with commit 92f1e9a4b31c ("clk: Detect failure to set
defaults") the clk driver for the PX30 would fail to probe for the
Odroid Go Advance. This patch is to remove the clock for the GPU from
the U-Boot specific devicetree, as that clock is not supported by the
U-Boot clk_px30 driver.

Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
---
 arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi b/arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi
index 00767d2abd..c330286bc5 100644
--- a/arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi
+++ b/arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi
@@ -9,8 +9,18 @@
 	};
 };
 
+/* U-Boot clk driver for px30 cannot set GPU_CLK */
 &cru {
 	u-boot,dm-pre-reloc;
+	assigned-clocks = <&cru PLL_NPLL>,
+		<&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
+		<&cru HCLK_BUS_PRE>, <&cru HCLK_PERI_PRE>,
+		<&cru PCLK_BUS_PRE>, <&cru PLL_CPLL>;
+
+	assigned-clock-rates = <1188000000>,
+		<200000000>, <200000000>,
+		<150000000>, <150000000>,
+		<100000000>, <17000000>;
 };
 
 &dmc {
-- 
2.25.1

Re: [PATCH 2/2] rockchip: board: remove SCLK_GPU from U-Boot DT

[Kever Yang]

Reviewed-by: Kever Yang <kever.yang@rock-chips.com>


Thanks,
- Kever

Chris Morgan <macroalpha82@gmail.com> 于2021年8月6日周五 上午12:49写道：
>
> From: Chris Morgan <macromorgan@hotmail.com>
>
> Starting with commit 92f1e9a4b31c ("clk: Detect failure to set
> defaults") the clk driver for the PX30 would fail to probe for the
> Odroid Go Advance. This patch is to remove the clock for the GPU from
> the U-Boot specific devicetree, as that clock is not supported by the
> U-Boot clk_px30 driver.
>
> Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
> ---
>  arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi | 10 ++++++++++
>  1 file changed, 10 insertions(+)
>
> diff --git a/arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi b/arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi
> index 00767d2abd..c330286bc5 100644
> --- a/arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi
> +++ b/arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi
> @@ -9,8 +9,18 @@
>         };
>  };
>
> +/* U-Boot clk driver for px30 cannot set GPU_CLK */
>  &cru {
>         u-boot,dm-pre-reloc;
> +       assigned-clocks = <&cru PLL_NPLL>,
> +               <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
> +               <&cru HCLK_BUS_PRE>, <&cru HCLK_PERI_PRE>,
> +               <&cru PCLK_BUS_PRE>, <&cru PLL_CPLL>;
> +
> +       assigned-clock-rates = <1188000000>,
> +               <200000000>, <200000000>,
> +               <150000000>, <150000000>,
> +               <100000000>, <17000000>;
>  };
>
>  &dmc {
> --
> 2.25.1
>