From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E8682C4338F for ; Thu, 12 Aug 2021 14:48:08 +0000 (UTC) Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id D059A60FC3 for ; Thu, 12 Aug 2021 14:48:07 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org D059A60FC3 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=denx.de Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=lists.denx.de Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id DBA7C82DDA; Thu, 12 Aug 2021 16:48:04 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=denx.de Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=denx.de; s=phobos-20191101; t=1628779685; bh=4a9gK/UnHyO2HIMj6NjmQEyOZ7LJDcR7SpTT3/T+sCc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From; b=Oh/HhE3fK/Hzj7+P4gty1vaSpe+EVnaSDxfi3B3U+MP2F68gjycdKlFbuIE/qqfEd P20ZXBA4PUuP5qxZvw+ZqOzk7eFjRoxWSYIl6izw7vbcGPsEBQtKO4EtCFhr1T3jiw kZHRgjS57RgkS515uhmDgsb3bd/5Gh1p1Jg60JXo1S7HveQgTBI6bvVQBbsDtlmpEL qLtStAplJnkGn53xx+gTgd7MHmP6syzzmoFIZVgJ1phsrm9vjcHIrspxPO+iJt1Xys v6yBlepwPMdi5PJkda1RnlYhzHEvbYHGcLmbHrwW7o/vkFrSRTZ9/1/I+s5VxvZW07 iL64CeRh7AMkg== Received: by phobos.denx.de (Postfix, from userid 109) id E57B782DBA; Thu, 12 Aug 2021 16:48:00 +0200 (CEST) Received: from mout-u-204.mailbox.org (mout-u-204.mailbox.org [IPv6:2001:67c:2050:1::465:204]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 2E0F582DAD for ; Thu, 12 Aug 2021 16:47:56 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=denx.de Authentication-Results: phobos.denx.de; spf=fail smtp.mailfrom=sr@denx.de Received: from smtp1.mailbox.org (smtp1.mailbox.org [80.241.60.240]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-384) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by mout-u-204.mailbox.org (Postfix) with ESMTPS id 4GlqL36VWrzQjmf; Thu, 12 Aug 2021 16:47:55 +0200 (CEST) Received: from smtp1.mailbox.org ([80.241.60.240]) by hefe.heinlein-support.de (hefe.heinlein-support.de [91.198.250.172]) (amavisd-new, port 10030) with ESMTP id 64TTXs7BsM4O; Thu, 12 Aug 2021 16:47:52 +0200 (CEST) From: Stefan Roese To: u-boot@lists.denx.de Cc: Wolfgang Denk , Rasmus Villemoes , sjg@chromium.org, trini@konsulko.com Subject: [PATCH v4 2/3] arm64: memset-arm64: Use simple memset when cache is disabled Date: Thu, 12 Aug 2021 16:47:50 +0200 Message-Id: <20210812144751.2563707-3-sr@denx.de> In-Reply-To: <20210812144751.2563707-1-sr@denx.de> References: <20210812144751.2563707-1-sr@denx.de> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Rspamd-Queue-Id: 7901318BB X-Rspamd-UID: 03908a X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean The optimized memset uses the dc opcode, which causes problems when the cache is disabled. This patch adds a check if the cache is disabled and uses a very simple memset implementation in this case. Otherwise the optimized version is used. Signed-off-by: Stefan Roese --- Changes in v4: - Use macros instead of register names, following the optimized code - Add zero size check Changes in v2: - New patch arch/arm/lib/memset-arm64.S | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/arch/arm/lib/memset-arm64.S b/arch/arm/lib/memset-arm64.S index 710f6f582cad..ee9f9a96cfe6 100644 --- a/arch/arm/lib/memset-arm64.S +++ b/arch/arm/lib/memset-arm64.S @@ -11,6 +11,7 @@ * */ +#include #include "asmdefs.h" #define dstin x0 @@ -25,6 +26,37 @@ ENTRY (memset) PTR_ARG (0) SIZE_ARG (2) + /* + * The optimized memset uses the dc opcode, which causes problems + * when the cache is disabled. Let's check if the cache is disabled + * and use a very simple memset implementation in this case. Otherwise + * jump to the optimized version. + */ + switch_el x6, 3f, 2f, 1f +3: mrs x6, sctlr_el3 + b 0f +2: mrs x6, sctlr_el2 + b 0f +1: mrs x6, sctlr_el1 +0: + tst x6, #CR_C + bne 9f + + /* + * A very "simple" memset implementation without the use of the + * dc opcode. Can be run with caches disabled. + */ + mov x3, #0x0 + cmp count, x3 /* check for zero length */ + beq 8f +4: strb valw, [dstin, x3] + add x3, x3, #0x1 + cmp count, x3 + bne 4b +8: ret +9: + + /* Here the optimized memset version starts */ dup v0.16B, valw add dstend, dstin, count -- 2.32.0