From: Eugen Hristev <eugen.hristev@microchip.com>
To: <u-boot@lists.denx.de>
Cc: <eugen.hristev@microchip.com>, <mihai.sain@microchip.com>
Subject: [PATCH 2/4] ARM: dts: at91: sama5d2_icp: cosmetic arrangement of the nodes
Date: Tue, 17 Aug 2021 13:29:23 +0300 [thread overview]
Message-ID: <20210817102925.62787-2-eugen.hristev@microchip.com> (raw)
In-Reply-To: <20210817102925.62787-1-eugen.hristev@microchip.com>
Reorder the nodes following the kernel rules: nodes in a range are sorted
by ascending bus address, and when referenced by phandle, are ordered
alphabetically.
Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
---
arch/arm/dts/at91-sama5d2_icp-u-boot.dtsi | 23 +++++++++++----------
arch/arm/dts/at91-sama5d2_icp.dts | 25 ++++++++++++-----------
2 files changed, 25 insertions(+), 23 deletions(-)
diff --git a/arch/arm/dts/at91-sama5d2_icp-u-boot.dtsi b/arch/arm/dts/at91-sama5d2_icp-u-boot.dtsi
index 68c27f229f..b45de978c2 100644
--- a/arch/arm/dts/at91-sama5d2_icp-u-boot.dtsi
+++ b/arch/arm/dts/at91-sama5d2_icp-u-boot.dtsi
@@ -13,34 +13,35 @@
};
};
-&sdmmc0 {
+&pinctrl_mikrobus1_uart {
u-boot,dm-pre-reloc;
};
-&uart0 { /* mikrobus1 uart */
+&pinctrl_qspi1_sck_cs_default {
u-boot,dm-pre-reloc;
};
-&pinctrl_sdmmc0_default {
+&pinctrl_qspi1_dat_default {
u-boot,dm-pre-reloc;
};
-&pinctrl_mikrobus1_uart {
+&pinctrl_sdmmc0_default {
u-boot,dm-pre-reloc;
};
-&pinctrl_qspi1_sck_cs_default {
+&qspi1 {
u-boot,dm-pre-reloc;
+
+ flash@0 {
+ u-boot,dm-pre-reloc;
+ };
};
-&pinctrl_qspi1_dat_default {
+&sdmmc0 {
u-boot,dm-pre-reloc;
};
-&qspi1 {
+&uart0 { /* mikrobus1 uart */
u-boot,dm-pre-reloc;
-
- flash@0 {
- u-boot,dm-pre-reloc;
- };
};
+
diff --git a/arch/arm/dts/at91-sama5d2_icp.dts b/arch/arm/dts/at91-sama5d2_icp.dts
index 2c6e91c1c7..44522197ff 100644
--- a/arch/arm/dts/at91-sama5d2_icp.dts
+++ b/arch/arm/dts/at91-sama5d2_icp.dts
@@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+ OR MIT
/*
* at91-sama5d2_icp.dts - Device Tree file for SAMA5D2 ICP board
- * SAMA5D2 Industrial Connectivity Board
+ * SAMA5D2 Industrial Connectivity Platform
*
* Copyright (c) 2018, Microchip Technology Inc.
* 2018, Eugen Hristev <eugen.hristev@microchip.com>
@@ -48,16 +48,16 @@
};
};
- uart0: serial@f801c000 { /* mikrobus1 uart */
+ macb0: ethernet@f8008000 {
pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_mikrobus1_uart>;
+ pinctrl-0 = <&pinctrl_macb0_rmii &pinctrl_macb0_phy_irq &pinctrl_macb0_rst>;
+ phy-mode = "internal";
status = "okay";
};
- macb0: ethernet@f8008000 {
+ uart0: serial@f801c000 { /* mikrobus1 uart */
pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_macb0_rmii &pinctrl_macb0_phy_irq &pinctrl_macb0_rst>;
- phy-mode = "internal";
+ pinctrl-0 = <&pinctrl_mikrobus1_uart>;
status = "okay";
};
@@ -85,6 +85,7 @@
pagesize = <16>;
};
};
+
pioA: gpio@fc038000 {
status = "okay";
pinctrl {
@@ -124,6 +125,12 @@
bias-pull-up;
};
+ pinctrl_mikrobus1_uart: mikrobus1_uart {
+ pinmux = <PIN_PB26__URXD0>,
+ <PIN_PB27__UTXD0>;
+ bias-disable;
+ };
+
pinctrl_qspi1_sck_cs_default: qspi1_sck_cs_default {
pinmux = <PIN_PA6__QSPI1_SCK>,
<PIN_PA11__QSPI1_CS>;
@@ -148,12 +155,6 @@
<PIN_PA13__SDMMC0_CD>;
bias-disable;
};
-
- pinctrl_mikrobus1_uart: mikrobus1_uart {
- pinmux = <PIN_PB26__URXD0>,
- <PIN_PB27__UTXD0>;
- bias-disable;
- };
};
};
};
--
2.25.1
next prev parent reply other threads:[~2021-08-17 10:30 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-08-17 10:29 [PATCH 1/4] ARM: dts: at91: sama5d2_icp: add QSPI1 device Eugen Hristev
2021-08-17 10:29 ` Eugen Hristev [this message]
2021-08-17 10:29 ` [PATCH 3/4] ARM: dts: at91: sama5d2: fix dtc warning for ohci and ehci Eugen Hristev
2021-08-20 6:25 ` Alexander Dahl
2021-08-17 10:29 ` [PATCH 4/4] configs: sama5d2: add qspi config for QSPI1 Eugen Hristev
2021-09-07 9:25 ` [PATCH 1/4] ARM: dts: at91: sama5d2_icp: add QSPI1 device Eugen.Hristev
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