From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.2 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_SANE_2 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 97E79C4338F for ; Sun, 22 Aug 2021 11:36:08 +0000 (UTC) Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id B258361057 for ; Sun, 22 Aug 2021 11:36:07 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org B258361057 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=nic.cz Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=lists.denx.de Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id EA68880796; Sun, 22 Aug 2021 13:36:03 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=nic.cz Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (1024-bit key; secure) header.d=nic.cz header.i=@nic.cz header.b="sVsBnrsE"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id EB4208023C; Sun, 22 Aug 2021 13:36:01 +0200 (CEST) Received: from mail.nic.cz (lists.nic.cz [IPv6:2001:1488:800:400::400]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id D7FA780796 for ; Sun, 22 Aug 2021 13:35:55 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=nic.cz Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=marek.behun@nic.cz Received: from thinkpad (unknown [172.20.6.87]) by mail.nic.cz (Postfix) with ESMTPSA id 2CD6E1408B0; Sun, 22 Aug 2021 13:35:55 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=nic.cz; s=default; t=1629632155; bh=Mb5PkIsmHQnL3eY+Ele+quN3VL6Pi/1D5TVu8S2zOEM=; h=Date:From:To; b=sVsBnrsEf8A6/iDKeKhGP7AUj32BFlObLFdqEwFnnOLJypL8Y2WcqGJs4MmyWdsCD rcnLxVO69H0CmAwweGsnUKd3uygHW5pnowOKinZI9Py9TFiLCQYFqm+2T/ESAU3mrB iT4h3qkRNmzZxAZP0qopx1PlxM+FUbXnd1gZ/1S0= Date: Sun, 22 Aug 2021 13:35:54 +0200 From: Marek =?UTF-8?B?QmVow7pu?= To: pali@kernel.org Cc: Tom Rini , u-boot@lists.denx.de, Stefan Roese Subject: Re: [PATCH 4/9] mvebu: ddr: Rename CONFIG_DDR_FIXED_SIZE to CONFIG_SYS_SDRAM_SIZE Message-ID: <20210822133554.55b24206@thinkpad> In-Reply-To: <20210821175019.24180-4-trini@konsulko.com> References: <20210821175019.24180-1-trini@konsulko.com> <20210821175019.24180-4-trini@konsulko.com> X-Mailer: Claws Mail 3.18.0 (GTK+ 2.24.33; x86_64-pc-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean + pali, who can tell whether this won't break how the code is aligned with upstream mv-ddr On Sat, 21 Aug 2021 13:50:14 -0400 Tom Rini wrote: > We have a number of CONFIG symbols to express the fixed size of system > memory. For now, rename CONFIG_DDR_FIXED_SIZE to CONFIG_SYS_SDRAM_SIZE > and adjust usage to match that CONFIG_SYS_SDRAM_SIZE expects the entire > size rather than MiB. >=20 > Cc: Marek Beh=C3=BAn > Cc: Stefan Roese > Signed-off-by: Tom Rini > --- > drivers/ddr/marvell/axp/ddr3_axp.h | 4 ++-- > include/configs/maxbcm.h | 4 +++- > include/configs/theadorable.h | 4 +++- > 3 files changed, 8 insertions(+), 4 deletions(-) >=20 > diff --git a/drivers/ddr/marvell/axp/ddr3_axp.h b/drivers/ddr/marvell/axp= /ddr3_axp.h > index 270691e9bcd3..970651f87029 100644 > --- a/drivers/ddr/marvell/axp/ddr3_axp.h > +++ b/drivers/ddr/marvell/axp/ddr3_axp.h > @@ -19,10 +19,10 @@ > #define FAR_END_DIMM_ADDR 0x50 > #define MAX_DIMM_ADDR 0x60 > =20 > -#ifndef CONFIG_DDR_FIXED_SIZE > +#ifndef CONFIG_SYS_SDRAM_SIZE > #define SDRAM_CS_SIZE 0xFFFFFFF > #else > -#define SDRAM_CS_SIZE (CONFIG_DDR_FIXED_SIZE - 1) > +#define SDRAM_CS_SIZE ((CONFIG_SYS_SDRAM_SIZE >> 10) - 1) > #endif > #define SDRAM_CS_BASE 0x0 > #define SDRAM_DIMM_SIZE 0x80000000 > diff --git a/include/configs/maxbcm.h b/include/configs/maxbcm.h > index fc2393204bec..5098f12f5425 100644 > --- a/include/configs/maxbcm.h > +++ b/include/configs/maxbcm.h > @@ -6,6 +6,8 @@ > #ifndef _CONFIG_DB_MV7846MP_GP_H > #define _CONFIG_DB_MV7846MP_GP_H > =20 > +#include > + > /* > * High Level Configuration Options (easy to change) > */ > @@ -65,7 +67,7 @@ > /* SPL related SPI defines */ > =20 > /* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */ > -#define CONFIG_DDR_FIXED_SIZE (1 << 20) /* 1GiB */ > +#define CONFIG_SYS_SDRAM_SIZE SZ_1G > #define CONFIG_BOARD_ECC_SUPPORT /* this board supports ECC */ > =20 > #endif /* _CONFIG_DB_MV7846MP_GP_H */ > diff --git a/include/configs/theadorable.h b/include/configs/theadorable.h > index 760713d3ef87..abc48ff44ca5 100644 > --- a/include/configs/theadorable.h > +++ b/include/configs/theadorable.h > @@ -6,6 +6,8 @@ > #ifndef _CONFIG_THEADORABLE_H > #define _CONFIG_THEADORABLE_H > =20 > +#include > + > /* > * High Level Configuration Options (easy to change) > */ > @@ -93,6 +95,6 @@ > #define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4) > =20 > /* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */ > -#define CONFIG_DDR_FIXED_SIZE (2 << 20) /* 2GiB */ > +#define CONFIG_SYS_SDRAM_SIZE SZ_2G > =20 > #endif /* _CONFIG_THEADORABLE_H */