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[2603:6081:7b01:cbda:9442:b45e:57c1:d916]) by smtp.gmail.com with ESMTPSA id d68sm95986qke.19.2021.09.07.13.27.33 (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 07 Sep 2021 13:27:34 -0700 (PDT) Date: Tue, 7 Sep 2021 16:27:32 -0400 From: Tom Rini To: Jan Kiszka , nm@ti.com Cc: Lokesh Vutla , u-boot@lists.denx.de, Grygorii Strashko , "Su, Bao Cheng (RC-CN DF FA R&D)" Subject: Re: [u-boot PATCH] arm: mach-k3: am6_init: Prioritize MSMC traffic over DDR in NAVSS Northbridge Message-ID: <20210907202732.GW12964@bill-the-cat> References: <20200130080503.28657-1-rogerq@ti.com> <3ff739a1-9e7b-4136-70f7-063ac6a21350@siemens.com> <99a3fa4a-adc4-3e0b-a0df-5996b80e47b5@siemens.com> <70b14156-d4f9-45e3-3466-8f89d83da1b2@siemens.com> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha512; protocol="application/pgp-signature"; boundary="MdJ3p2aQbVp3YFXz" Content-Disposition: inline In-Reply-To: <70b14156-d4f9-45e3-3466-8f89d83da1b2@siemens.com> X-Clacks-Overhead: GNU Terry Pratchett User-Agent: Mutt/1.9.4 (2018-02-28) X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean --MdJ3p2aQbVp3YFXz Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Tue, Sep 07, 2021 at 09:41:23PM +0200, Jan Kiszka wrote: > On 02.09.21 08:36, Jan Kiszka wrote: > > On 28.07.21 11:10, Jan Kiszka wrote: > >> On 30.01.20 09:05, Roger Quadros wrote: > >>> NB0 is bridge to SRAM and NB1 is bridge to DDR. > >>> > >>> To ensure that SRAM transfers are not stalled due to > >>> delays during DDR refreshes, SRAM traffic should be higher > >>> priority (threadmap=3D2) than DDR traffic (threadmap=3D0). > >>> > >>> This patch does just that. > >>> > >>> This is required to fix ICSSG TX lock-ups due to delays in > >>> MSMC transfers due to incorrect Northbridge configuration. > >>> > >>> Signed-off-by: Roger Quadros > >>> Acked-by: Andrew F. Davis > >>> Acked-by: Tomi Valkeinen > >>> Acked-by: Benoit Parrot > >>> --- > >>> arch/arm/mach-k3/am6_init.c | 14 ++++++++++++++ > >>> arch/arm/mach-k3/include/mach/am6_hardware.h | 7 +++++++ > >>> 2 files changed, 21 insertions(+) > >>> > >>> diff --git a/arch/arm/mach-k3/am6_init.c b/arch/arm/mach-k3/am6_init.c > >>> index 8d107b870b..9379b95bdb 100644 > >>> --- a/arch/arm/mach-k3/am6_init.c > >>> +++ b/arch/arm/mach-k3/am6_init.c > >>> @@ -86,6 +86,18 @@ static void store_boot_index_from_rom(void) > >>> bootindex =3D *(u32 *)(CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX); > >>> } > >>> =20 > >>> +static void setup_am654_navss_northbridge(void) > >>> +{ > >>> + /* > >>> + * NB0 is bridge to SRAM and NB1 is bridge to DDR. > >>> + * To ensure that SRAM transfers are not stalled due to > >>> + * delays during DDR refreshes, SRAM traffic should be higher > >>> + * priority (threadmap=3D2) than DDR traffic (threadmap=3D0). > >>> + */ > >>> + writel(0x2, NAVSS0_NBSS_NB0_CFG_BASE + NAVSS_NBSS_THREADMAP); > >>> + writel(0x0, NAVSS0_NBSS_NB1_CFG_BASE + NAVSS_NBSS_THREADMAP); > >>> +} > >>> + > >>> void board_init_f(ulong dummy) > >>> { > >>> #if defined(CONFIG_K3_LOAD_SYSFW) || defined(CONFIG_K3_AM654_DDRSS) > >>> @@ -101,6 +113,8 @@ void board_init_f(ulong dummy) > >>> /* Make all control module registers accessible */ > >>> ctrl_mmr_unlock(); > >>> =20 > >>> + setup_am654_navss_northbridge(); > >>> + > >>> #ifdef CONFIG_CPU_V7R > >>> disable_linefill_optimization(); > >>> setup_k3_mpu_regions(); > >>> diff --git a/arch/arm/mach-k3/include/mach/am6_hardware.h b/arch/arm/= mach-k3/include/mach/am6_hardware.h > >>> index 6df7631545..45a5b31c52 100644 > >>> --- a/arch/arm/mach-k3/include/mach/am6_hardware.h > >>> +++ b/arch/arm/mach-k3/include/mach/am6_hardware.h > >>> @@ -47,4 +47,11 @@ > >>> /* MCU SCRATCHPAD usage */ > >>> #define TI_SRAM_SCRATCH_BOARD_EEPROM_START CONFIG_SYS_K3_MCU_SCRATCH= PAD_BASE > >>> =20 > >>> +/* NAVSS Northbridge config */ > >>> +#define NAVSS0_NBSS_NB0_CFG_BASE 0x03802000 > >>> +#define NAVSS0_NBSS_NB1_CFG_BASE 0x03803000 > >>> + > >>> +#define NAVSS_NBSS_PID 0x0 > >>> +#define NAVSS_NBSS_THREADMAP 0x10 > >>> + > >>> #endif /* __ASM_ARCH_AM6_HARDWARE_H */ > >>> > >> > >> This was never merged, not even commented on (only apparently rejected > >> in patchwork) - but it is crucial as we now found out: > >> > >> prueth will quickly stall when these priorities are not applied, at > >> least with SR1.0-based AM65x designs. And you probably know what else > >> could go wrong. Please clarify and merge, possibly reducing the scope = to > >> SR1.0 if you can confirm that SR2.0 cannot be affected by design (I can > >> only say this based on few practical experiments here). > >> > >> If it was good for several TI SDK releases by now, at least something > >> similar should be good for upstream as well, I believe. > >> > >=20 > > Ping. We need at least some confirmation on what is actually needed. > > Then, if you do not like to add it to the generic path, it would be easy > > for us to carry it in the IOT2050 board init only - with the appropriate > > condition check. >=20 > Did some more experiments on SR2 silicon, and while I'm not seeing > stalls without this patch there, iperf tests with prueth show high retry > rates and, thus, about 10% worse throughput. So it seems to be required > for newer silicon as well. At this point, I'd really appreciate it if someone from within TI can chime in here as I expect someone must suspect something here, thanks! --=20 Tom --MdJ3p2aQbVp3YFXz Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iQGzBAABCgAdFiEEGjx/cOCPqxcHgJu/FHw5/5Y0tywFAmE3yykACgkQFHw5/5Y0 tywkOQv/TiPAyTV2O0Cm4yYRXVJO+lWlHYTCU2lr88LLGv5inygwZVh7bJIQM3M1 kX0TLh4JCf6DICzYDCDPWpyifYy9kHExu9uL1NAp8PT1Z3VNHMmhTfp4NxbUX2nG EbVELiC+JOP97RTgEytfo76CQZkdO8sieZMkN9T55wlmL3opW/As6TSHTdOmebsJ ITBNeOYZmI6rWVq3sU8E5ylDX2ol4KD0k2zzsFEd48DBCRJYoYC9vaD1bc35c032 YmM8yaRTNKxqaP8KXuLNb5l5kGoKrGnLaTJJGp7jqqyfxu0G6EST1eMgrQLg9LGQ jmAdSiiz4yj3JcLoil/U+uUJ5WY/yK9qncTj5ccqBjBhI4g5rUuEFU5qXS9U8Lon 15R+GrCNHXyCTygN15odp8vX0ovxhPi+aP8zhFHRSlv4gkHnTO33zJ/R2dnsUtIG qUAzXZkWfiQxlSNBn/fxaGhUgpr0FCXGHP6Pt92ucPPeRsNRYnVPOWVg8rQLaXSw +K/vPYyT =+GT6 -----END PGP SIGNATURE----- --MdJ3p2aQbVp3YFXz--