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[79.146.82.133]) by smtp.gmail.com with ESMTPSA id n66sm3635159wmn.2.2021.09.10.00.56.06 (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 10 Sep 2021 00:56:07 -0700 (PDT) From: "Jorge Ramirez-Ortiz, Foundries" X-Google-Original-From: "Jorge Ramirez-Ortiz, Foundries" Date: Fri, 10 Sep 2021 09:56:06 +0200 To: Michal Simek Cc: "Jorge Ramirez-Ortiz, Foundries" , u-boot@lists.denx.de Subject: Re: cdns_wdt: who enables the clock Message-ID: <20210910075606.GA13123@trex> References: <20210908153930.GA15019@trex> <0266772a-b833-0b4d-91ba-0971f38816f3@monstr.eu> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <0266772a-b833-0b4d-91ba-0971f38816f3@monstr.eu> User-Agent: Mutt/1.9.4 (2018-02-28) X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean On 10/09/21, Michal Simek wrote: > Hi, > > On 9/8/21 5:39 PM, Jorge Ramirez-Ortiz, Foundries wrote: > > Hi Michal > > > > The *linux* cadence_wdt driver for the watchdog enables the clock that > > controls its behaviour. However this is not done in the U-boot > > driver; I dont think it is safe to assume that the clock will be active. > > do you know why is the driver making that assumption? and how to > > enable the clock? > > > > Also, I am not sure it is either safe to assume that the WDT IP will > > be enabled; IMO during probe we should do something like this > > (otherwise the AXI bus will complain and fault the boot) > > > > static int cdns_wdt_probe(struct udevice *dev) > > { > > - debug("%s: Probing wdt%u\n", __func__, dev_seq(dev)); > > + u32 rst = 0; > > + > > + /* release WDT from reset */ > > + rst = readl(0xFD1A0100) & ~BIT(15); > > + writel(rst, 0xFD1A0100); > > + > > + debug("%s: Probing wdt%u)\n", __func__, dev_seq(dev)); > > > > return 0; > > } > > If reset should be perform it should be done via > drivers/reset/reset-zynqmp.c ok > > It means when you define it in DT you will get reset. makes sene > > I am ok to wire all resets for all IPs to make sure that they are in > proper state but this has to be tested first. all right. but yes this particular case was tested. > > Thanks, > Michal > > -- > Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91 > w: www.monstr.eu p: +42-0-721842854 > Maintainer of Linux kernel - Xilinx Microblaze > Maintainer of Linux kernel - Xilinx Zynq ARM and ZynqMP ARM64 SoCs > U-Boot custodian - Xilinx Microblaze/Zynq/ZynqMP/Versal SoCs >