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From: Marek Vasut <marex@denx.de>
To: u-boot@lists.denx.de
Cc: Marek Vasut <marex@denx.de>,
	Marcel Ziswiler <marcel.ziswiler@toradex.com>,
	Max Krummenacher <max.krummenacher@toradex.com>,
	Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
Subject: [PATCH] ARM: dts: imx8mm-verdin: Set PHY mode to RGMII-ID
Date: Sun, 12 Sep 2021 00:43:18 +0200	[thread overview]
Message-ID: <20210911224318.99111-1-marex@denx.de> (raw)

Since c6df0e2ffdc ("net: phy: micrel: add support for DLL setup on ksz9131")
the Micrel PHY driver correctly configures the delay register. The Verdin PHY
is RGMII-ID, so reflect that in DT, otherwise the ethernet no longer works.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Cc: Max Krummenacher <max.krummenacher@toradex.com>
Cc: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
---
 arch/arm/dts/imx8mm-verdin.dts | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/dts/imx8mm-verdin.dts b/arch/arm/dts/imx8mm-verdin.dts
index fb0756d6e19..ac2a4b69d3c 100644
--- a/arch/arm/dts/imx8mm-verdin.dts
+++ b/arch/arm/dts/imx8mm-verdin.dts
@@ -160,7 +160,7 @@
 &fec1 {
 	fsl,magic-packet;
 	phy-handle = <&ethphy0>;
-	phy-mode = "rgmii";
+	phy-mode = "rgmii-id";
 	phy-supply = <&reg_ethphy>;
 	pinctrl-names = "default", "sleep";
 	pinctrl-0 = <&pinctrl_fec1>;
-- 
2.33.0


             reply	other threads:[~2021-09-11 22:43 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-09-11 22:43 Marek Vasut [this message]
2021-09-11 22:53 ` [PATCH] ARM: dts: imx8mm-verdin: Set PHY mode to RGMII-ID Marcel Ziswiler
2021-09-11 22:57   ` Marek Vasut
2021-10-07 14:12 ` sbabic
2021-10-07 23:56   ` Marcel Ziswiler
2021-10-08  0:13     ` Marcel Ziswiler
2021-10-08  0:22       ` Marek Vasut

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