From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 45643C433EF for ; Mon, 20 Sep 2021 23:30:41 +0000 (UTC) Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 797EF60F21 for ; Mon, 20 Sep 2021 23:30:40 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 797EF60F21 Authentication-Results: mail.kernel.org; dmarc=fail (p=quarantine dis=none) header.from=microchip.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=lists.denx.de Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id EF83983257; Tue, 21 Sep 2021 01:30:20 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=fail (p=quarantine dis=none) header.from=microchip.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=microchip.com header.i=@microchip.com header.b="oZGxK+ey"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 83C0480224; Tue, 21 Sep 2021 01:29:01 +0200 (CEST) Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id A595182E67 for ; Tue, 21 Sep 2021 01:28:56 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=microchip.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=Dan.Sneddon@microchip.com DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1632180536; x=1663716536; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=+wyg7R+YHFFmduRFIuU32047/Cu0d41JdgqQPvXBM98=; b=oZGxK+eyjgEhkFP3A4axzM1SUdZuvmlJvmwz5he7Gopn/zCyM9bzFDrk 5hhCNX8AOlasv6nJtKi9IyiKav0O4C/VU7cH3vZC265kOw3j6G/v8J9GG h4OqgcIBXWwDXItCmqYOUK0KKSrxpvUX7sdyMlwNpnp87wAe2fDw9+Bs/ +ByDLdNV6fni3sJp/iAqES89c1PxGTfIZP35fSjBwYHp9MHvb/7bPdlft wq0w0gbYJnSra8567de68O+fpsYGz7Lqnjpx/QgzRQs1G4jyDlkM8uMhp xOGfjtH6/f1CpYIl4WWf9usaGYG0wF2n8Sf4CJTRRUlnnrZ/NiBanJKkl g==; IronPort-SDR: qlbPsI3xtKOY2ncPHrwRihT4Dhb1e3+JVBrY60reZqpPCyjfbZL2qT4LtnYuULto4LDI9dA9Ml LBk0q/o3+HNF7ZdmdRDFS7XPsgZBbVnIynzY9PLVHrjARp4tom4FOQl4tURXv17+02WUKjSC3A vG5keAqJsUFg1A+OmhUr80lxJVjOQt9giq73UUUCfu2Fcm+RKimQODcVzd95yK4dNBHNkm62fs I0IOnmv0cvxxdi6vcsR2g26fxnR7ZVSjTT+s6nYn3aT1fCu6ZzwNYxD7L7q9bRbkKGLxDnbp5Q w6JSyWqzEnhEC+P3bQaCruW3 X-IronPort-AV: E=Sophos;i="5.85,309,1624345200"; d="scan'208";a="137283211" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa3.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 20 Sep 2021 16:28:52 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.14; Mon, 20 Sep 2021 16:28:51 -0700 Received: from dan-linux.microchip.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2176.14 via Frontend Transport; Mon, 20 Sep 2021 16:28:51 -0700 From: Dan Sneddon To: CC: Dan Sneddon Subject: [PATCH 1/3] pwm: Add PWM driver for SAMA5D2 Date: Mon, 20 Sep 2021 16:28:44 -0700 Message-ID: <20210920232846.25954-2-dan.sneddon@microchip.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210920232846.25954-1-dan.sneddon@microchip.com> References: <20210920232846.25954-1-dan.sneddon@microchip.com> MIME-Version: 1.0 Content-Type: text/plain X-Mailman-Approved-At: Tue, 21 Sep 2021 01:30:14 +0200 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean Add support for the PWM found on the SAMA5D2 family of devices. Signed-off-by: Dan Sneddon --- drivers/pwm/Kconfig | 6 ++ drivers/pwm/Makefile | 1 + drivers/pwm/pwm-at91.c | 207 +++++++++++++++++++++++++++++++++++++++++ 3 files changed, 214 insertions(+) create mode 100644 drivers/pwm/pwm-at91.c diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig index cf7f4c6840..691bbcd469 100644 --- a/drivers/pwm/Kconfig +++ b/drivers/pwm/Kconfig @@ -91,3 +91,9 @@ config PWM_TI_EHRPWM default y help PWM driver support for the EHRPWM controller found on TI SOCs. + +config PWM_AT91 + bool "Enable support for PWM found on AT91 SoC's" + depends on DM_PWM && ARCH_AT91 + help + Support for PWM hardware on AT91 based SoC. diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile index 10d244bfb7..6cdcbdb996 100644 --- a/drivers/pwm/Makefile +++ b/drivers/pwm/Makefile @@ -21,3 +21,4 @@ obj-$(CONFIG_PWM_SIFIVE) += pwm-sifive.o obj-$(CONFIG_PWM_TEGRA) += tegra_pwm.o obj-$(CONFIG_PWM_SUNXI) += sunxi_pwm.o obj-$(CONFIG_PWM_TI_EHRPWM) += pwm-ti-ehrpwm.o +obj-$(CONFIG_PWM_AT91) += pwm-at91.o diff --git a/drivers/pwm/pwm-at91.c b/drivers/pwm/pwm-at91.c new file mode 100644 index 0000000000..95597aee55 --- /dev/null +++ b/drivers/pwm/pwm-at91.c @@ -0,0 +1,207 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * PWM support for Microchip AT91 architectures. + * + * Copyright (C) 2021 Microchip Technology Inc. and its subsidiaries + * + * Author: Dan Sneddon + * + * Based on drivers/pwm/pwm-atmel.c from Linux. + */ +#include +#include +#include +#include +#include +#include +#include + +#define PERIOD_BITS 16 +#define PWM_MAX_PRES 10 +#define NSEC_PER_SEC 1000000000L + +#define PWM_ENA 0x04 +#define PWM_CHANNEL_OFFSET 0x20 +#define PWM_CMR 0x200 +#define PWM_CMR_CPRE_MSK GENMASK(3, 0) +#define PWM_CMR_CPOL BIT(9) +#define PWM_CDTY 0x204 +#define PWM_CPRD 0x20C + +struct at91_pwm_priv { + void __iomem *base; + struct clk pclk; + u32 clkrate; +}; + +static int at91_pwm_calculate_cprd_and_pres(struct udevice *dev, + unsigned long clkrate, + uint period_ns, uint duty_ns, + unsigned long *cprd, u32 *pres) +{ + u64 cycles = period_ns; + int shift; + + /* Calculate the period cycles and prescale value */ + cycles *= clkrate; + do_div(cycles, NSEC_PER_SEC); + + /* + * The register for the period length is period_bits bits wide. + * So for each bit the number of clock cycles is wider divide the input + * clock frequency by two using pres and shift cprd accordingly. + */ + shift = fls(cycles) - PERIOD_BITS; + + if (shift > PWM_MAX_PRES) { + return -EINVAL; + } else if (shift > 0) { + *pres = shift; + cycles >>= *pres; + } else { + *pres = 0; + } + + *cprd = cycles; + + return 0; +} + +static void at91_pwm_calculate_cdty(uint period_ns, uint duty_ns, + unsigned long clkrate, unsigned long cprd, + u32 pres, unsigned long *cdty) +{ + u64 cycles = duty_ns; + + cycles *= clkrate; + do_div(cycles, NSEC_PER_SEC); + cycles >>= pres; + *cdty = cprd - cycles; +} + +/** + * Returns: channel status after set operation + */ +static bool at91_pwm_set(void __iomem *base, uint channel, bool enable) +{ + u32 val, cur_status; + + val = ioread32(base + PWM_ENA); + cur_status = !!(val & BIT(channel)); + + /* if channel is already in that state, do nothing */ + if (!(enable ^ cur_status)) + return cur_status; + + if (enable) + val |= BIT(channel); + else + val &= ~(BIT(channel)); + + iowrite32(val, base + PWM_ENA); + + return cur_status; +} + +static int at91_pwm_set_enable(struct udevice *dev, uint channel, bool enable) +{ + struct at91_pwm_priv *priv = dev_get_priv(dev); + + at91_pwm_set(priv->base, channel, enable); + + return 0; +} + +static int at91_pwm_set_config(struct udevice *dev, uint channel, + uint period_ns, uint duty_ns) +{ + struct at91_pwm_priv *priv = dev_get_priv(dev); + unsigned long cprd, cdty; + u32 pres, val; + int channel_enabled; + int ret; + + ret = at91_pwm_calculate_cprd_and_pres(dev, priv->clkrate, period_ns, + duty_ns, &cprd, &pres); + if (ret) + return ret; + + at91_pwm_calculate_cdty(period_ns, duty_ns, priv->clkrate, cprd, pres, &cdty); + + /* disable the channel */ + channel_enabled = at91_pwm_set(priv->base, channel, false); + + /* It is necessary to preserve CPOL, inside CMR */ + val = ioread32(priv->base + (channel * PWM_CHANNEL_OFFSET) + PWM_CMR); + val = (val & ~PWM_CMR_CPRE_MSK) | (pres & PWM_CMR_CPRE_MSK); + iowrite32(val, priv->base + (channel * PWM_CHANNEL_OFFSET) + PWM_CMR); + + iowrite32(cprd, priv->base + (channel * PWM_CHANNEL_OFFSET) + PWM_CPRD); + + iowrite32(cdty, priv->base + (channel * PWM_CHANNEL_OFFSET) + PWM_CDTY); + + /* renable the channel if needed */ + if (channel_enabled) + at91_pwm_set(priv->base, channel, true); + + return 0; +} + +static int at91_pwm_set_invert(struct udevice *dev, uint channel, + bool polarity) +{ + struct at91_pwm_priv *priv = dev_get_priv(dev); + u32 val; + + val = ioread32(priv->base + (channel * PWM_CHANNEL_OFFSET) + PWM_CMR); + if (polarity) + val |= PWM_CMR_CPOL; + else + val &= ~PWM_CMR_CPOL; + iowrite32(val, priv->base + (channel * PWM_CHANNEL_OFFSET) + PWM_CMR); + + return 0; +} + +static int at91_pwm_probe(struct udevice *dev) +{ + struct at91_pwm_priv *priv = dev_get_priv(dev); + int ret; + + priv->base = dev_read_addr_ptr(dev); + if (!priv->base) + return -EINVAL; + + ret = clk_get_by_index(dev, 0, &priv->pclk); + if (ret) + return ret; + + /* clocks aren't ref-counted so just enabled them once here */ + ret = clk_enable(&priv->pclk); + if (ret) + return ret; + + priv->clkrate = clk_get_rate(&priv->pclk); + + return ret; +} + +static const struct pwm_ops at91_pwm_ops = { + .set_config = at91_pwm_set_config, + .set_enable = at91_pwm_set_enable, + .set_invert = at91_pwm_set_invert, +}; + +static const struct udevice_id at91_pwm_of_match[] = { + { .compatible = "atmel,sama5d2-pwm" }, + { } +}; + +U_BOOT_DRIVER(at91_pwm) = { + .name = "at91_pwm", + .id = UCLASS_PWM, + .of_match = at91_pwm_of_match, + .probe = at91_pwm_probe, + .priv_auto = sizeof(struct at91_pwm_priv), + .ops = &at91_pwm_ops, +}; -- 2.17.1