From: "Marek Behún" <kabel@kernel.org>
To: Stefan Roese <sr@denx.de>
Cc: u-boot@lists.denx.de, pali@kernel.org,
"Marek Behún" <marek.behun@nic.cz>
Subject: [PATCH u-boot-marvell v2 3/6] arm: a37xx: pci: Do not automatically enable bus mastering on PCI Bridge
Date: Sun, 26 Sep 2021 00:54:43 +0200 [thread overview]
Message-ID: <20210925225446.1872-4-kabel@kernel.org> (raw)
In-Reply-To: <20210925225446.1872-1-kabel@kernel.org>
From: Pali Rohár <pali@kernel.org>
Now that PCI Bridge is working for the PCIe Root Port, U-Boot's PCI_PNP
code automatically enables memory access and bus mastering when needed.
We do not need to enable it when setting the HW up.
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Marek Behún <marek.behun@nic.cz>
---
drivers/pci/pci-aardvark.c | 6 ------
1 file changed, 6 deletions(-)
diff --git a/drivers/pci/pci-aardvark.c b/drivers/pci/pci-aardvark.c
index 692210ded9..8c025dc45d 100644
--- a/drivers/pci/pci-aardvark.c
+++ b/drivers/pci/pci-aardvark.c
@@ -910,12 +910,6 @@ static int pcie_advk_setup_hw(struct pcie_advk *pcie)
if (pcie_advk_wait_for_link(pcie))
return -ENXIO;
- reg = advk_readl(pcie, PCIE_CORE_CMD_STATUS_REG);
- reg |= PCIE_CORE_CMD_MEM_ACCESS_EN |
- PCIE_CORE_CMD_IO_ACCESS_EN |
- PCIE_CORE_CMD_MEM_IO_REQ_EN;
- advk_writel(pcie, reg, PCIE_CORE_CMD_STATUS_REG);
-
return 0;
}
--
2.32.0
next prev parent reply other threads:[~2021-09-25 22:55 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-09-25 22:54 [PATCH u-boot-marvell v2 0/6] A3720 PCIe enhancements Marek Behún
2021-09-25 22:54 ` [PATCH u-boot-marvell v2 1/6] arm: a37xx: pci: Fix pcie_advk_link_up() Marek Behún
2021-10-08 6:20 ` Stefan Roese
2021-09-25 22:54 ` [PATCH u-boot-marvell v2 2/6] arm: a37xx: pci: Add support for accessing PCI Bridge on root bus Marek Behún
2021-10-05 21:55 ` Pali Rohár
2021-10-08 6:20 ` Stefan Roese
2021-10-08 6:21 ` Stefan Roese
2021-09-25 22:54 ` Marek Behún [this message]
2021-10-08 6:21 ` [PATCH u-boot-marvell v2 3/6] arm: a37xx: pci: Do not automatically enable bus mastering on PCI Bridge Stefan Roese
2021-09-25 22:54 ` [PATCH u-boot-marvell v2 4/6] arm: a37xx: pci: Handle propagation of CRSSVE bit from PCIe Root Port Marek Behún
2021-10-08 6:21 ` Stefan Roese
2021-09-25 22:54 ` [PATCH u-boot-marvell v2 5/6] arm: a37xx: pci: Cosmetic change Marek Behún
2021-10-08 6:21 ` Stefan Roese
2021-09-25 22:54 ` [PATCH u-boot-marvell v2 6/6] arm: a37xx: pci: Update private structure documentation Marek Behún
2021-10-08 6:22 ` Stefan Roese
2021-10-08 9:18 ` [PATCH u-boot-marvell v2 0/6] A3720 PCIe enhancements Stefan Roese
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20210925225446.1872-4-kabel@kernel.org \
--to=kabel@kernel.org \
--cc=marek.behun@nic.cz \
--cc=pali@kernel.org \
--cc=sr@denx.de \
--cc=u-boot@lists.denx.de \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox