From: "Marek Behún" <kabel@kernel.org>
To: Stefan Roese <sr@denx.de>
Cc: u-boot@lists.denx.de, pali@kernel.org,
"Marek Behún" <marek.behun@nic.cz>
Subject: [PATCH u-boot-marvell v2 6/6] arm: a37xx: pci: Update private structure documentation
Date: Sun, 26 Sep 2021 00:54:46 +0200 [thread overview]
Message-ID: <20210925225446.1872-7-kabel@kernel.org> (raw)
In-Reply-To: <20210925225446.1872-1-kabel@kernel.org>
From: Marek Behún <marek.behun@nic.cz>
There were several changes for this structure but the documentation was
not changed at the time. Fix this.
Signed-off-by: Marek Behún <marek.behun@nic.cz>
---
drivers/pci/pci-aardvark.c | 17 +++++++++--------
1 file changed, 9 insertions(+), 8 deletions(-)
diff --git a/drivers/pci/pci-aardvark.c b/drivers/pci/pci-aardvark.c
index b4f350ca2c..414872ed35 100644
--- a/drivers/pci/pci-aardvark.c
+++ b/drivers/pci/pci-aardvark.c
@@ -186,14 +186,15 @@
/**
* struct pcie_advk - Advk PCIe controller state
*
- * @reg_base: The base address of the register space.
- * @first_busno: This driver supports multiple PCIe controllers.
- * first_busno stores the bus number of the PCIe root-port
- * number which may vary depending on the PCIe setup
- * (PEX switches etc).
- * @sec_busno: sec_busno stores the bus number for the device behind
- * the PCIe root-port
- * @device: The pointer to PCI uclass device.
+ * @base: The base address of the register space.
+ * @first_busno: Bus number of the PCIe root-port.
+ * This may vary depending on the PCIe setup.
+ * @sec_busno: Bus number for the device behind the PCIe root-port.
+ * @dev: The pointer to PCI uclass device.
+ * @reset_gpio: GPIO descriptor for PERST.
+ * @cfgcache: Buffer for emulation of PCIe Root Port's PCI Bridge registers
+ * that are not available on Aardvark.
+ * @cfgcrssve: For CRSSVE emulation.
*/
struct pcie_advk {
void *base;
--
2.32.0
next prev parent reply other threads:[~2021-09-25 22:56 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-09-25 22:54 [PATCH u-boot-marvell v2 0/6] A3720 PCIe enhancements Marek Behún
2021-09-25 22:54 ` [PATCH u-boot-marvell v2 1/6] arm: a37xx: pci: Fix pcie_advk_link_up() Marek Behún
2021-10-08 6:20 ` Stefan Roese
2021-09-25 22:54 ` [PATCH u-boot-marvell v2 2/6] arm: a37xx: pci: Add support for accessing PCI Bridge on root bus Marek Behún
2021-10-05 21:55 ` Pali Rohár
2021-10-08 6:20 ` Stefan Roese
2021-10-08 6:21 ` Stefan Roese
2021-09-25 22:54 ` [PATCH u-boot-marvell v2 3/6] arm: a37xx: pci: Do not automatically enable bus mastering on PCI Bridge Marek Behún
2021-10-08 6:21 ` Stefan Roese
2021-09-25 22:54 ` [PATCH u-boot-marvell v2 4/6] arm: a37xx: pci: Handle propagation of CRSSVE bit from PCIe Root Port Marek Behún
2021-10-08 6:21 ` Stefan Roese
2021-09-25 22:54 ` [PATCH u-boot-marvell v2 5/6] arm: a37xx: pci: Cosmetic change Marek Behún
2021-10-08 6:21 ` Stefan Roese
2021-09-25 22:54 ` Marek Behún [this message]
2021-10-08 6:22 ` [PATCH u-boot-marvell v2 6/6] arm: a37xx: pci: Update private structure documentation Stefan Roese
2021-10-08 9:18 ` [PATCH u-boot-marvell v2 0/6] A3720 PCIe enhancements Stefan Roese
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