From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A6CB8C433EF for ; Sun, 26 Sep 2021 17:49:37 +0000 (UTC) Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 9954760FC2 for ; Sun, 26 Sep 2021 17:49:36 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 9954760FC2 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=lists.denx.de Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 7D0A7835D7; Sun, 26 Sep 2021 19:49:29 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="NPFVVWxQ"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 9024C8348D; Sun, 26 Sep 2021 19:49:22 +0200 (CEST) Received: from mail-ed1-x531.google.com (mail-ed1-x531.google.com [IPv6:2a00:1450:4864:20::531]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id DF3EE8348D for ; Sun, 26 Sep 2021 19:49:17 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=dsankouski@gmail.com Received: by mail-ed1-x531.google.com with SMTP id ee50so59152177edb.13 for ; Sun, 26 Sep 2021 10:49:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=WvYHIHoJZ1tboaAruhru/9hm6WTa6dx3qZXdcTy9k0M=; b=NPFVVWxQQKsZFWairmuzHbNnXPlY1zJTVXGy1lE6wualCi59dk3m9EavDFNe16mVz9 Kqjmm0vEpY3OXSwn2u2XuCc6RMSgQl2PQPt83PVshGJ/H6aNhVHVXJuLch6RGsIA5rg+ OkIpW9CWX9wXG00PewvKaW0mYwvcd/B9nOrSw6POHSAbeW4SYeRSaEgtQBKbbjzaVQ2b KfQzbNpJCSJoiVW9OXwNLbaB8qSVVufdNyVsBMC5GeT6S6zx21Bx+c+yZN8UwNGuvLz8 wWUPE2nE+b6BbOtz1hVh2SHHTthlW9TeIis0QY1pjAVDY8wRgphTinXO1GhNui3r8V6E f6Lw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=WvYHIHoJZ1tboaAruhru/9hm6WTa6dx3qZXdcTy9k0M=; b=kiU/TzXTPM8SkXyqRLm3nv0MUONT68cWHKXzw4yMqGNejamyu3qbWkbJnN/dW3+UJY vL0itQXkV9FTLX/wgy9pcii43+oIrtBOVOtM1pQBl1uXTFPglbOf4eTkaKQwiLcW3Ha8 31fxWxLsQeKwL0/31UF37cJ3q9HVuV1YI2IbBI/r0EiKWlovqeQQNA4DfLv3IOzKa7ot wgbkxRmbcJlBYCSaXRaF+R0w3ahkDxpq8P+Js/u3cfzOkT3pZUFq5He4ClmQ6Rwzv17k EzSuyx2eX7qX5s+s+3iye8iAPdPNyYXutFVEVF2IOptZLztJnZaaSbFUuGztYvoT9LXl oP4w== X-Gm-Message-State: AOAM530LWq+4yAHoTqrV5xBMRqoA89MeevG3E5LkdR1daJdSZO7BrEPn 3DYnyuiAedxo/2ljVGxzT/n4tiDS09K5NQ== X-Google-Smtp-Source: ABdhPJxa1FiTy2MfduRh0xs/VJ7gZw05vsdfq8onYPehQ/hWpyf465FpzROsI03WmqGzPSaPC+E9qw== X-Received: by 2002:a50:d6d8:: with SMTP id l24mr18556573edj.297.1632678557308; Sun, 26 Sep 2021 10:49:17 -0700 (PDT) Received: from localhost.localdomain ([46.216.16.109]) by smtp.gmail.com with ESMTPSA id k12sm7612384ejk.63.2021.09.26.10.49.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 26 Sep 2021 10:49:17 -0700 (PDT) From: dsankouski@gmail.com To: u-boot@lists.denx.de Cc: Dzmitry Sankouski , Ramon Fried , Tom Rini , Stephan Gerhold Subject: [PATCH 5/6 v2] SoC: qcom: add support for SDM845 Date: Sun, 26 Sep 2021 20:49:05 +0300 Message-Id: <20210926174905.12810-2-dsankouski@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210926174905.12810-1-dsankouski@gmail.com> References: <20210926174905.12810-1-dsankouski@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean From: Dzmitry Sankouski Hi-end qualcomm chip, introduced in late 2017. Mostly used in flagship phones and tablets of 2018. Features: - arm64 arch - total of 8 Kryo 385 Gold / Silver cores - Hexagon 685 DSP - Adreno 630 GPU Tested only as second-stage bootloader. Signed-off-by: Dzmitry Sankouski Cc: Ramon Fried Cc: Tom Rini Cc: Stephan Gerhold --- Changes for v2: - refactor sdm845.dtsi. arch/arm/dts/sdm845.dtsi | 116 ++++++++++++++++++ arch/arm/mach-snapdragon/Kconfig | 4 + arch/arm/mach-snapdragon/Makefile | 4 + .../include/mach/sysmap-sdm845.h | 42 +++++++ arch/arm/mach-snapdragon/init_sdm845.c | 82 +++++++++++++ arch/arm/mach-snapdragon/sysmap-sdm845.c | 31 +++++ include/configs/sdm845.h | 33 +++++ 7 files changed, 312 insertions(+) create mode 100644 arch/arm/dts/sdm845.dtsi create mode 100644 arch/arm/mach-snapdragon/include/mach/sysmap-sdm845.h create mode 100644 arch/arm/mach-snapdragon/init_sdm845.c create mode 100644 arch/arm/mach-snapdragon/sysmap-sdm845.c create mode 100644 include/configs/sdm845.h diff --git a/arch/arm/dts/sdm845.dtsi b/arch/arm/dts/sdm845.dtsi new file mode 100644 index 0000000000..1185b71216 --- /dev/null +++ b/arch/arm/dts/sdm845.dtsi @@ -0,0 +1,116 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Qualcomm SDM845 chip device tree source + * + * (C) Copyright 2021 Dzmitry Sankouski + * + */ + +/dts-v1/; + +#include "skeleton64.dtsi" + +/ { + soc: soc { + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0 0xffffffff>; + compatible = "simple-bus"; + + gcc: clock-controller@100000 { + u-boot,dm-pre-reloc; + compatible = "qcom,gcc-sdm845"; + reg = <0x100000 0x1f0000>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + + gpio_north: gpio_north@3900000 { + u-boot,dm-pre-reloc; + #gpio-cells = <2>; + compatible = "qcom,sdm845-pinctrl"; + reg = <0x3900000 0x400000>; + gpio-count = <150>; + gpio-controller; + gpio-ranges = <&gpio_north 0 0 150>; + gpio-bank-name = "soc_north."; + }; + + tlmm_north: pinctrl_north@3900000 { + u-boot,dm-pre-reloc; + compatible = "qcom,tlmm-sdm845"; + reg = <0x3900000 0x400000>; + gpio-count = <150>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&tlmm_north 0 0 150>; + + /* DEBUG UART */ + qup_uart9: qup-uart9-default { + pinmux { + pins = "GPIO_4", "GPIO_5"; + function = "qup9"; + }; + }; + }; + + debug_uart: serial@a84000 { + compatible = "qcom,msm-geni-uart"; + reg = <0xa84000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk"; + clocks = <&gcc 0x58>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_uart9>; + qcom,wrapper-core = <0x8a>; + status = "disabled"; + }; + + spmi@c440000 { + compatible = "qcom,spmi-pmic-arb"; + reg = <0xc440000 0x1100>, + <0xc600000 0x2000000>, + <0xe600000 0x100000>; + reg-names = "cnfg", "core", "obsrvr"; + #address-cells = <0x1>; + #size-cells = <0x1>; + + qcom,revid@100 { + compatible = "qcom,qpnp-revid"; + reg = <0x100 0x100>; + }; + + pmic0: pm8998@0 { + compatible = "qcom,spmi-pmic"; + reg = <0x0 0x1>; + #address-cells = <0x1>; + #size-cells = <0x1>; + + pm8998_pon: pm8998_pon@800 { + compatible = "qcom,pm8998-pwrkey"; + reg = <0x800 0x100>; + #gpio-cells = <2>; + gpio-controller; + gpio-bank-name = "pm8998_key."; + }; + + pm8998_gpios: pm8998_gpios@c000 { + compatible = "qcom,pm8998-gpio"; + reg = <0xc000 0x1a00>; + gpio-controller; + gpio-count = <21>; + #gpio-cells = <2>; + gpio-bank-name = "pm8998."; + }; + }; + + pmic1: pm8998@1 { + compatible = "qcom,spmi-pmic"; + reg = <0x1 0x0>; + #address-cells = <0x2>; + #size-cells = <0x0>; + }; + }; + }; +}; diff --git a/arch/arm/mach-snapdragon/Kconfig b/arch/arm/mach-snapdragon/Kconfig index 0ec74fa5d3..1a6a608967 100644 --- a/arch/arm/mach-snapdragon/Kconfig +++ b/arch/arm/mach-snapdragon/Kconfig @@ -9,6 +9,10 @@ config SYS_MALLOC_F_LEN config SPL_SYS_MALLOC_F_LEN default 0x2000 +config SDM845 + bool "Qualcomm Snapdragon 845 SoC" + default n + choice prompt "Snapdragon board select" diff --git a/arch/arm/mach-snapdragon/Makefile b/arch/arm/mach-snapdragon/Makefile index 709919fce4..962855eb8c 100644 --- a/arch/arm/mach-snapdragon/Makefile +++ b/arch/arm/mach-snapdragon/Makefile @@ -2,6 +2,9 @@ # # (C) Copyright 2015 Mateusz Kulikowski +obj-$(CONFIG_SDM845) += clock-sdm845.o +obj-$(CONFIG_SDM845) += sysmap-sdm845.o +obj-$(CONFIG_SDM845) += init_sdm845.o obj-$(CONFIG_TARGET_DRAGONBOARD820C) += clock-apq8096.o obj-$(CONFIG_TARGET_DRAGONBOARD820C) += sysmap-apq8096.o obj-$(CONFIG_TARGET_DRAGONBOARD410C) += clock-apq8016.o @@ -12,3 +15,4 @@ obj-y += dram.o obj-y += pinctrl-snapdragon.o obj-y += pinctrl-apq8016.o obj-y += pinctrl-apq8096.o +obj-$(CONFIG_SDM845) += pinctrl-sdm845.o diff --git a/arch/arm/mach-snapdragon/include/mach/sysmap-sdm845.h b/arch/arm/mach-snapdragon/include/mach/sysmap-sdm845.h new file mode 100644 index 0000000000..7165985bcd --- /dev/null +++ b/arch/arm/mach-snapdragon/include/mach/sysmap-sdm845.h @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Qualcomm SDM845 sysmap + * + * (C) Copyright 2021 Dzmitry Sankouski + */ +#ifndef _MACH_SYSMAP_SDM845_H +#define _MACH_SYSMAP_SDM845_H + +#define TLMM_BASE_ADDR (0x1010000) + +/* Strength (sdc1) */ +#define SDC1_HDRV_PULL_CTL_REG (TLMM_BASE_ADDR + 0x0012D000) + +/* Clocks: (from CLK_CTL_BASE) */ +#define GPLL0_STATUS (0x0000) +#define APCS_GPLL_ENA_VOTE (0x52000) +#define APCS_CLOCK_BRANCH_ENA_VOTE (0x52004) + +#define SDCC2_BCR (0x14000) /* block reset */ +#define SDCC2_APPS_CBCR (0x14004) /* branch control */ +#define SDCC2_AHB_CBCR (0x14008) +#define SDCC2_CMD_RCGR (0x1400c) +#define SDCC2_CFG_RCGR (0x14010) +#define SDCC2_M (0x14014) +#define SDCC2_N (0x14018) +#define SDCC2_D (0x1401C) + +#define RCG2_CFG_REG 0x4 +#define M_REG 0x8 +#define N_REG 0xc +#define D_REG 0x10 + +#define SE9_AHB_CBCR (0x25004) +#define SE9_UART_APPS_CBCR (0x29004) +#define SE9_UART_APPS_CMD_RCGR (0x18148) +#define SE9_UART_APPS_CFG_RCGR (0x1814C) +#define SE9_UART_APPS_M (0x18150) +#define SE9_UART_APPS_N (0x18154) +#define SE9_UART_APPS_D (0x18158) + +#endif diff --git a/arch/arm/mach-snapdragon/init_sdm845.c b/arch/arm/mach-snapdragon/init_sdm845.c new file mode 100644 index 0000000000..5f53c21947 --- /dev/null +++ b/arch/arm/mach-snapdragon/init_sdm845.c @@ -0,0 +1,82 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Common init part for boards based on SDM845 + * + * (C) Copyright 2021 Dzmitry Sankouski + */ + +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +int dram_init(void) +{ + return fdtdec_setup_mem_size_base(); +} + +void reset_cpu(void) +{ + psci_system_reset(); +} + +__weak int board_init(void) +{ + return 0; +} + +/* Check for vol- and power buttons */ +__weak int misc_init_r(void) +{ + struct udevice *pon; + struct gpio_desc resin; + int node, ret; + + ret = uclass_get_device_by_name(UCLASS_GPIO, "pm8998_pon@800", &pon); + if (ret < 0) { + printf("Failed to find PMIC pon node. Check device tree\n"); + return 0; + } + + node = fdt_subnode_offset(gd->fdt_blob, dev_of_offset(pon), + "key_vol_down"); + if (node < 0) { + printf("Failed to find key_vol_down node. Check device tree\n"); + return 0; + } + if (gpio_request_by_name_nodev(offset_to_ofnode(node), "gpios", 0, + &resin, 0)) { + printf("Failed to request key_vol_down button.\n"); + return 0; + } + if (dm_gpio_get_value(&resin)) { + env_set("key_vol_down", "1"); + printf("Volume down button pressed\n"); + } else { + env_set("key_vol_down", "0"); + } + + node = fdt_subnode_offset(gd->fdt_blob, dev_of_offset(pon), + "key_power"); + if (node < 0) { + printf("Failed to find key_power node. Check device tree\n"); + return 0; + } + if (gpio_request_by_name_nodev(offset_to_ofnode(node), "gpios", 0, + &resin, 0)) { + printf("Failed to request key_power button.\n"); + return 0; + } + if (dm_gpio_get_value(&resin)) { + env_set("key_power", "1"); + printf("Power button pressed\n"); + } else { + env_set("key_power", "0"); + } + + return 0; +} diff --git a/arch/arm/mach-snapdragon/sysmap-sdm845.c b/arch/arm/mach-snapdragon/sysmap-sdm845.c new file mode 100644 index 0000000000..721ac41166 --- /dev/null +++ b/arch/arm/mach-snapdragon/sysmap-sdm845.c @@ -0,0 +1,31 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Qualcomm SDM845 memory map + * + * (C) Copyright 2021 Dzmitry Sankouski + */ + +#include +#include + +static struct mm_region sdm845_mem_map[] = { + { + .virt = 0x0UL, /* Peripheral block */ + .phys = 0x0UL, /* Peripheral block */ + .size = 0x10000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + .virt = 0x80000000UL, /* DDR */ + .phys = 0x80000000UL, /* DDR */ + .size = 0x200000000UL, /* 8GiB - maximum allowed memory */ + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, { + /* List terminator */ + 0, + } +}; + +struct mm_region *mem_map = sdm845_mem_map; diff --git a/include/configs/sdm845.h b/include/configs/sdm845.h new file mode 100644 index 0000000000..c77d0acac6 --- /dev/null +++ b/include/configs/sdm845.h @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Configuration file for boards, based on Qualcomm SDM845 chip + * + * (C) Copyright 2021 Dzmitry Sankouski + */ + +#ifndef __CONFIGS_SDM845_H +#define __CONFIGS_SDM845_H + +#include +#include + +#define CONFIG_SYS_LOAD_ADDR 0x80000000 +#define CONFIG_SYS_BAUDRATE_TABLE { 115200, 230400, 460800, 921600 } + +/* Generic Timer Definitions */ +#define COUNTER_FREQUENCY 19000000 + +#define EXTRA_ENV_SETTINGS \ + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "loadaddr=0x80000000\0" + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + SZ_8M) +#define CONFIG_SYS_BOOTM_LEN SZ_64M + +/* Monitor Command Prompt */ +#define CONFIG_SYS_CBSIZE 512 +#define CONFIG_SYS_MAXARGS 64 + +#endif -- 2.20.1