From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 30191C433FE for ; Mon, 4 Oct 2021 22:57:30 +0000 (UTC) Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id DB0666126A for ; Mon, 4 Oct 2021 22:57:28 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org DB0666126A Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=lists.denx.de Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 3778D8033A; Tue, 5 Oct 2021 00:57:26 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id 7C62280D1C; Tue, 5 Oct 2021 00:57:24 +0200 (CEST) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by phobos.denx.de (Postfix) with ESMTP id 7CEFE8032F for ; Tue, 5 Oct 2021 00:57:20 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=andre.przywara@arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 621EC6D; Mon, 4 Oct 2021 15:57:19 -0700 (PDT) Received: from slackpad.fritz.box (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id A8A913F70D; Mon, 4 Oct 2021 15:57:18 -0700 (PDT) Date: Mon, 4 Oct 2021 23:56:57 +0100 From: Andre Przywara To: Manuel Dipolt Cc: u-boot , jagan Subject: Re: [PATCH] sunxi: h3: enable clock support for r_pio gpios Message-ID: <20211004235603.49701eee@slackpad.fritz.box> In-Reply-To: <775585477.1144891.1627316388716.JavaMail.zimbra@robart.cc> References: <775585477.1144891.1627316388716.JavaMail.zimbra@robart.cc> Organization: Arm Ltd. X-Mailer: Claws Mail 3.17.1 (GTK+ 2.24.31; x86_64-slackware-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean On Mon, 26 Jul 2021 18:19:48 +0200 (CEST) Manuel Dipolt wrote: Hi Manuel, > This patch enables clock for the r_pio gpios for the h3 Thanks for the patch, but can you say what this is needed for or what it fixes? Also this patch looks mangled, the leading spaces in the diff context are gone, and tabs were converted to a single space - which makes this impossible to apply. Can you fix your settting, or find a better email client (git send-email, for instance)? Cheers, Andre > Signed-off-by: Manuel Dipolt > --- > drivers/clk/sunxi/Makefile | 1 + > drivers/clk/sunxi/clk_h3-r.c | 51 ++++++++++++++++++++++++++++++++++++ > drivers/gpio/sunxi_gpio.c | 9 +++++++ > 3 files changed, 61 insertions(+) > create mode 100644 drivers/clk/sunxi/clk_h3-r.c > > diff --git a/drivers/clk/sunxi/Makefile b/drivers/clk/sunxi/Makefile > index 36fb2aeb56..e93fe3c2f3 100644 > --- a/drivers/clk/sunxi/Makefile > +++ b/drivers/clk/sunxi/Makefile > @@ -15,5 +15,6 @@ obj-$(CONFIG_CLK_SUN8I_R40) += clk_r40.o > obj-$(CONFIG_CLK_SUN8I_V3S) += clk_v3s.o > obj-$(CONFIG_CLK_SUN9I_A80) += clk_a80.o > obj-$(CONFIG_CLK_SUN8I_H3) += clk_h3.o > +obj-$(CONFIG_CLK_SUN8I_H3) += clk_h3-r.o > obj-$(CONFIG_CLK_SUN50I_H6) += clk_h6.o > obj-$(CONFIG_CLK_SUN50I_A64) += clk_a64.o > diff --git a/drivers/clk/sunxi/clk_h3-r.c b/drivers/clk/sunxi/clk_h3-r.c > new file mode 100644 > index 0000000000..a314e37b87 > --- /dev/null > +++ b/drivers/clk/sunxi/clk_h3-r.c > @@ -0,0 +1,51 @@ > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) > +/* > + * Copyright (C) 2021 RobArt GmbH > + * Author: Manuel Dipolt > + */ > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +static struct ccu_clk_gate h3_r_gates[] = { > + [CLK_APB0_PIO] = GATE(0x28, BIT(0)), > +}; > + > +static struct ccu_reset h3_r_resets[] = { > + [RST_APB0_IR] = RESET(0x0b0, BIT(2)), > + [RST_APB0_TIMER] = RESET(0x0b0, BIT(3)), > + [RST_APB0_UART] = RESET(0x0b0, BIT(4)), > + [RST_APB0_I2C] = RESET(0x0b0, BIT(6)), > +}; > + > +static const struct ccu_desc h3_r_ccu_desc = { > + .gates = h3_r_gates, > + .resets = h3_r_resets, > +}; > + > +static int h3_r_clk_bind(struct udevice *dev) > +{ > + return sunxi_reset_bind(dev, ARRAY_SIZE(h3_r_resets)); > +} > + > +static const struct udevice_id h3_r_ccu_ids[] = { > + { .compatible = "allwinner,sun8i-h3-r-ccu", > + .data = (ulong)&h3_r_ccu_desc }, > + { } > +}; > + > +U_BOOT_DRIVER(clk_sun8i_h3_r) = { > + .name = "sun8i_h3-r_ccu", > + .id = UCLASS_CLK, > + .of_match = h3_r_ccu_ids, > + .priv_auto_alloc_size = sizeof(struct ccu_priv), > + .ops = &sunxi_clk_ops, > + .probe = sunxi_clk_probe, > + .bind = h3_r_clk_bind, > +}; > + > diff --git a/drivers/gpio/sunxi_gpio.c b/drivers/gpio/sunxi_gpio.c > index cbed8d42b7..b505be4065 100644 > --- a/drivers/gpio/sunxi_gpio.c > +++ b/drivers/gpio/sunxi_gpio.c > @@ -14,6 +14,7 @@ > #include > #include > #include > +#include > #include > #include > #include > @@ -262,6 +263,14 @@ static int gpio_sunxi_probe(struct udevice *dev) > { > struct sunxi_gpio_platdata *plat = dev_get_platdata(dev); > struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev); > + struct clk gate_clk; > + int ret; > + > + ret = clk_get_by_name(dev, "apb", &gate_clk); > + > + if (!ret) > + clk_enable(&gate_clk); > + > > /* Tell the uclass how many GPIOs we have */ > if (plat) {