From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id CDBCDC433EF for ; Tue, 12 Oct 2021 11:20:23 +0000 (UTC) Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 09FC160698 for ; Tue, 12 Oct 2021 11:20:23 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 09FC160698 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=kernel.org Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=lists.denx.de Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id E2B758372B; Tue, 12 Oct 2021 13:20:20 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=kernel.org header.i=@kernel.org header.b="m+GvvEm9"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 8198582982; Tue, 12 Oct 2021 13:20:18 +0200 (CEST) Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 4EBFB83721 for ; Tue, 12 Oct 2021 13:20:15 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=pali@kernel.org Received: by mail.kernel.org (Postfix) with ESMTPSA id B1B2E61078; Tue, 12 Oct 2021 11:20:08 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1634037608; bh=BQaAQFFEa+DzReABWj4DdDGkzNAPpg1n4AjuTU7SdmY=; h=From:To:Cc:Subject:Date:From; b=m+GvvEm9vKAjz2J3xngl8q9JH2Jq+BpTtMygo5kFC9CD8io2SR10lAF4Y8p80V+x7 Tu81CGncjhEctUkgjIMijTH0svbMiL6+PTzcnK+Qf19lWKpOvC3wV7L0atxnpi6PrQ MNHh2/WGJmKGy/Wel36ZctHAPF9r839RBJH6mlxvoA6fBGuFKtpvD8XSD/oXCFqdPT oCFX9TAZtvgEZLsj4mQLzfgRVMTVpx7TxGYGA8EkzkBWBqDKFV80ibUEOZZUo0k1tF RzDSgNwRWH04e+kbsRP4nrWN/JD2ZU15CkKsB6sftx9pCO++x+pUx1BzLXpVEoN/an 9TW+/tjuQALWQ== Received: by pali.im (Postfix) id 3B62F5BC; Tue, 12 Oct 2021 13:20:06 +0200 (CEST) From: =?UTF-8?q?Pali=20Roh=C3=A1r?= To: Stefan Roese Cc: u-boot@lists.denx.de Subject: [PATCH] arm: a37xx: pci: Do not allow setting bars on PCI Bridge Date: Tue, 12 Oct 2021 13:19:19 +0200 Message-Id: <20211012111919.10918-1-pali@kernel.org> X-Mailer: git-send-email 2.20.1 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean PCI Bridge which represents Aardvark PCIe Root Port does not have configurable bars. So ensure that write operation to bars registers on PCI Bridge is noop and bars registers always contain zero address which indicates that bars are unsupported. After this change U-Boot 'pci bar 0.0.0' command does not show any allocated bars for PCI Bridge device. Signed-off-by: Pali Rohár Fixes: cb056005dc67 ("arm: a37xx: pci: Add support for accessing PCI Bridge on root bus") --- drivers/pci/pci-aardvark.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/pci/pci-aardvark.c b/drivers/pci/pci-aardvark.c index 38eff495ab1c..ade5ab056f84 100644 --- a/drivers/pci/pci-aardvark.c +++ b/drivers/pci/pci-aardvark.c @@ -581,6 +581,10 @@ static int pcie_advk_write_config(struct udevice *bus, pci_dev_t bdf, if (offset >= 0x10 && offset < 0x34) { data = pcie->cfgcache[(offset - 0x10) / 4]; data = pci_conv_size_to_32(data, value, offset, size); + /* This PCI bridge does not have configurable bars */ + if ((offset & ~3) == PCI_BASE_ADDRESS_0 || + (offset & ~3) == PCI_BASE_ADDRESS_1) + data = 0x0; pcie->cfgcache[(offset - 0x10) / 4] = data; } else if ((offset & ~3) == PCI_ROM_ADDRESS1) { data = advk_readl(pcie, PCIE_CORE_EXP_ROM_BAR_REG); -- 2.20.1