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From: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
To: <lukma@denx.de>, <sjg@chromium.org>, <trini@konsulko.com>,
	<mr.nuke.me@gmail.com>, <u-boot@lists.denx.de>
Cc: <joel@jms.id.au>, <ryan_chen@aspeedtech.com>,
	<johnny_huang@aspeedtech.com>
Subject: [PATCH next v6 09/12] ast2600: spl: Locate load buffer in DRAM space
Date: Fri, 15 Oct 2021 10:03:34 +0800	[thread overview]
Message-ID: <20211015020337.1024-10-chiawei_wang@aspeedtech.com> (raw)
In-Reply-To: <20211015020337.1024-1-chiawei_wang@aspeedtech.com>

Return CONFIG_SYS_LOAD_ADDR pointing to DRAM space for
spl_get_load_buffer() to allow generic SPL image loading
code (e.g. FIT and Ymodem) to store data in DRAM.

Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
---
 arch/arm/mach-aspeed/ast2600/spl.c | 9 +--------
 1 file changed, 1 insertion(+), 8 deletions(-)

diff --git a/arch/arm/mach-aspeed/ast2600/spl.c b/arch/arm/mach-aspeed/ast2600/spl.c
index 0d8cb29678..6c49d6aede 100644
--- a/arch/arm/mach-aspeed/ast2600/spl.c
+++ b/arch/arm/mach-aspeed/ast2600/spl.c
@@ -28,14 +28,7 @@ u32 spl_boot_device(void)
 
 struct image_header *spl_get_load_buffer(ssize_t offset, size_t size)
 {
-	/*
-	 * When boot from SPI, AST2600 already remap 0x00000000 ~ 0x0fffffff
-	 * to BMC SPI memory space 0x20000000 ~ 0x2fffffff. The next stage BL
-	 * has been located in SPI for XIP. In this case, the load buffer for
-	 * SPL image loading will be set to the remapped address of the next
-	 * BL instead of the DRAM space CONFIG_SYS_LOAD_ADDR
-	 */
-	return (struct image_header *)(CONFIG_SYS_TEXT_BASE);
+	return (struct image_header *)(CONFIG_SYS_LOAD_ADDR);
 }
 
 #ifdef CONFIG_SPL_OS_BOOT
-- 
2.17.1


  parent reply	other threads:[~2021-10-15  2:05 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-10-15  2:03 [PATCH next v6 00/12] aspeed: Support secure boot chain with FIT image verification Chia-Wei Wang
2021-10-15  2:03 ` [PATCH next v6 01/12] image: fit: Fix parameter name for hash algorithm Chia-Wei Wang
2021-10-15  2:03 ` [PATCH next v6 02/12] aspeed: ast2600: Enlarge SRAM size Chia-Wei Wang
2021-10-15  2:03 ` [PATCH next v6 03/12] clk: ast2600: Add YCLK control for HACE Chia-Wei Wang
2021-10-15  2:03 ` [PATCH next v6 04/12] crypto: aspeed: Add AST2600 HACE support Chia-Wei Wang
2021-10-15  2:03 ` [PATCH next v6 05/12] ARM: dts: ast2600: Add HACE to device tree Chia-Wei Wang
2021-10-15  2:03 ` [PATCH next v6 06/12] clk: ast2600: Add RSACLK control for ACRY Chia-Wei Wang
2021-10-15  2:03 ` [PATCH next v6 07/12] crypto: aspeed: Add AST2600 ACRY support Chia-Wei Wang
2021-10-18  3:06   ` ChiaWei Wang
2021-10-15  2:03 ` [PATCH next v6 08/12] ARM: dts: ast2600: Add ACRY to device tree Chia-Wei Wang
2021-10-15  2:03 ` Chia-Wei Wang [this message]
2021-10-15  2:03 ` [PATCH next v6 10/12] configs: ast2600-evb: Enable SPL FIT support Chia-Wei Wang
2021-10-15  2:03 ` [PATCH next v6 11/12] configs: aspeed: Make EXTRA_ENV_SETTINGS board specific Chia-Wei Wang
2021-10-15  2:03 ` [PATCH next v6 12/12] configs: ast2600: Boot kernel FIT in DRAM Chia-Wei Wang

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