From: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
To: <lukma@denx.de>, <sjg@chromium.org>, <trini@konsulko.com>,
<mr.nuke.me@gmail.com>, <u-boot@lists.denx.de>
Cc: <joel@jms.id.au>, <ryan_chen@aspeedtech.com>,
<johnny_huang@aspeedtech.com>
Subject: [PATCH next v6 08/12] ARM: dts: ast2600: Add ACRY to device tree
Date: Fri, 15 Oct 2021 10:03:33 +0800 [thread overview]
Message-ID: <20211015020337.1024-9-chiawei_wang@aspeedtech.com> (raw)
In-Reply-To: <20211015020337.1024-1-chiawei_wang@aspeedtech.com>
Add ACRY DTS node and enable it for AST2600 EVB.
Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
---
arch/arm/dts/ast2600-evb.dts | 5 +++++
arch/arm/dts/ast2600.dtsi | 9 +++++++++
2 files changed, 14 insertions(+)
diff --git a/arch/arm/dts/ast2600-evb.dts b/arch/arm/dts/ast2600-evb.dts
index adb80a30ef..05362d19bd 100644
--- a/arch/arm/dts/ast2600-evb.dts
+++ b/arch/arm/dts/ast2600-evb.dts
@@ -182,3 +182,8 @@
u-boot,dm-pre-reloc;
status = "okay";
};
+
+&acry {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
diff --git a/arch/arm/dts/ast2600.dtsi b/arch/arm/dts/ast2600.dtsi
index b8fe966c7d..31905fd208 100644
--- a/arch/arm/dts/ast2600.dtsi
+++ b/arch/arm/dts/ast2600.dtsi
@@ -195,6 +195,15 @@
status = "disabled";
};
+ acry: acry@1e6fa000 {
+ compatible = "aspeed,ast2600-acry";
+ reg = <0x1e6fa000 0x1000>,
+ <0x1e710000 0x10000>;
+ interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scu ASPEED_CLK_GATE_RSACLK>;
+ status = "disabled";
+ };
+
edac: sdram@1e6e0000 {
compatible = "aspeed,ast2600-sdram-edac";
reg = <0x1e6e0000 0x174>;
--
2.17.1
next prev parent reply other threads:[~2021-10-15 2:05 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-15 2:03 [PATCH next v6 00/12] aspeed: Support secure boot chain with FIT image verification Chia-Wei Wang
2021-10-15 2:03 ` [PATCH next v6 01/12] image: fit: Fix parameter name for hash algorithm Chia-Wei Wang
2021-10-15 2:03 ` [PATCH next v6 02/12] aspeed: ast2600: Enlarge SRAM size Chia-Wei Wang
2021-10-15 2:03 ` [PATCH next v6 03/12] clk: ast2600: Add YCLK control for HACE Chia-Wei Wang
2021-10-15 2:03 ` [PATCH next v6 04/12] crypto: aspeed: Add AST2600 HACE support Chia-Wei Wang
2021-10-15 2:03 ` [PATCH next v6 05/12] ARM: dts: ast2600: Add HACE to device tree Chia-Wei Wang
2021-10-15 2:03 ` [PATCH next v6 06/12] clk: ast2600: Add RSACLK control for ACRY Chia-Wei Wang
2021-10-15 2:03 ` [PATCH next v6 07/12] crypto: aspeed: Add AST2600 ACRY support Chia-Wei Wang
2021-10-18 3:06 ` ChiaWei Wang
2021-10-15 2:03 ` Chia-Wei Wang [this message]
2021-10-15 2:03 ` [PATCH next v6 09/12] ast2600: spl: Locate load buffer in DRAM space Chia-Wei Wang
2021-10-15 2:03 ` [PATCH next v6 10/12] configs: ast2600-evb: Enable SPL FIT support Chia-Wei Wang
2021-10-15 2:03 ` [PATCH next v6 11/12] configs: aspeed: Make EXTRA_ENV_SETTINGS board specific Chia-Wei Wang
2021-10-15 2:03 ` [PATCH next v6 12/12] configs: ast2600: Boot kernel FIT in DRAM Chia-Wei Wang
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