From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 84D8DC433EF for ; Fri, 15 Oct 2021 17:27:48 +0000 (UTC) Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id D803660E8B for ; Fri, 15 Oct 2021 17:27:47 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org D803660E8B Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=lists.denx.de Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id E95FB8386F; Fri, 15 Oct 2021 19:27:37 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=linux.intel.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id 2503D8048A; Fri, 15 Oct 2021 19:27:30 +0200 (CEST) Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 60A4C8385C for ; Fri, 15 Oct 2021 19:27:26 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=linux.intel.com Authentication-Results: phobos.denx.de; spf=none smtp.mailfrom=andriy.shevchenko@linux.intel.com X-IronPort-AV: E=McAfee;i="6200,9189,10138"; a="228236353" X-IronPort-AV: E=Sophos;i="5.85,376,1624345200"; d="scan'208";a="228236353" Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Oct 2021 10:27:23 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.85,376,1624345200"; d="scan'208";a="716574332" Received: from black.fi.intel.com ([10.237.72.28]) by fmsmga006.fm.intel.com with ESMTP; 15 Oct 2021 10:27:21 -0700 Received: by black.fi.intel.com (Postfix, from userid 1003) id 820ACF9; Fri, 15 Oct 2021 20:11:50 +0300 (EEST) From: Andy Shevchenko To: Andy Shevchenko , Bin Meng , Simon Glass , u-boot@lists.denx.de Subject: [PATCH v1 1/2] x86: tangier: Enable support for SD/SDIO family in the pinmux driver Date: Fri, 15 Oct 2021 20:11:46 +0300 Message-Id: <20211015171147.51948-1-andriy.shevchenko@linux.intel.com> X-Mailer: git-send-email 2.33.0 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean We would need to quirk out Card Detect case and for that we allow configuring SD/SDIO family of pins. Signed-off-by: Andy Shevchenko --- arch/x86/cpu/tangier/pinmux.c | 39 ++++++++++++++++++++++++++++++----- 1 file changed, 34 insertions(+), 5 deletions(-) diff --git a/arch/x86/cpu/tangier/pinmux.c b/arch/x86/cpu/tangier/pinmux.c index acf97e3af51d..8385167b2b6b 100644 --- a/arch/x86/cpu/tangier/pinmux.c +++ b/arch/x86/cpu/tangier/pinmux.c @@ -37,8 +37,9 @@ struct mrfld_family { .npins = (e) - (s) + 1, \ } -/* Now we only support I2C family of pins */ +/* Now we only support SD/SDIO and I2C families of pins */ static struct mrfld_family mrfld_families[] = { + MRFLD_FAMILY(3, 37, 56), MRFLD_FAMILY(7, 101, 114), }; @@ -125,6 +126,34 @@ static int mrfld_pinconfig_protected(unsigned int pin, u32 mask, u32 bits) return ret; } +static int mrfld_pinconfig(unsigned int pin, u32 mask, u32 bits) +{ + struct mrfld_pinctrl *pinctrl; + struct udevice *dev; + void __iomem *bufcfg; + u32 v, value; + int ret; + + ret = syscon_get_by_driver_data(X86_SYSCON_PINCONF, &dev); + if (ret) + return ret; + + pinctrl = dev_get_priv(dev); + + bufcfg = mrfld_get_bufcfg(pinctrl, pin); + if (!bufcfg) + return -EINVAL; + + value = readl(bufcfg); + v = (value & ~mask) | (bits & mask); + writel(v, bufcfg); + + debug("v: 0x%x p: 0x%x bits: %d, mask: %d bufcfg: 0x%p\n", + v, (u32)bufcfg, bits, mask, bufcfg); + + return 0; +} + static int mrfld_pinctrl_cfg_pin(ofnode pin_node) { bool is_protected; @@ -133,10 +162,7 @@ static int mrfld_pinctrl_cfg_pin(ofnode pin_node) u32 mask; int ret; - /* For now we only support just protected Family of pins */ is_protected = ofnode_read_bool(pin_node, "protected"); - if (!is_protected) - return -ENOTSUPP; pad_offset = ofnode_read_s32_default(pin_node, "pad-offset", -1); if (pad_offset == -1) @@ -152,7 +178,10 @@ static int mrfld_pinctrl_cfg_pin(ofnode pin_node) if (mode & ~mask) return -ENOTSUPP; - ret = mrfld_pinconfig_protected(pad_offset, mask, mode); + if (is_protected) + ret = mrfld_pinconfig_protected(pad_offset, mask, mode); + else + ret = mrfld_pinconfig(pad_offset, mask, mode); return ret; } -- 2.33.0