From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 07621C433EF for ; Fri, 22 Oct 2021 14:23:42 +0000 (UTC) Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 6A48760E96 for ; Fri, 22 Oct 2021 14:23:41 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 6A48760E96 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=kernel.org Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=lists.denx.de Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 4AF02834E8; Fri, 22 Oct 2021 16:23:30 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=kernel.org header.i=@kernel.org header.b="Ut097QtU"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 5157A83508; Fri, 22 Oct 2021 16:23:04 +0200 (CEST) Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id D12CF8350A for ; Fri, 22 Oct 2021 16:22:50 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=pali@kernel.org Received: by mail.kernel.org (Postfix) with ESMTPSA id A26A96109E; Fri, 22 Oct 2021 14:22:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1634912568; bh=c/IEP25YsrVrYICM/o4zesUgbQaslHgr6ViB5v3IO/c=; h=From:To:Cc:Subject:Date:From; b=Ut097QtUJRp3uhMv94TC2IODwBzIkiM0efbLV3y5nrh4ta2G5lDo9nOQ3SzPQR7IF QOfXcFepBtflmEQXwsFteLl9gA0cX1XchA6m81xDp2XFJW5SjW+5mrL4zcv5hgya9y pN2if0COqhy9dZhSLdQYgeXoGC2LddfRV2Q6QjXDAurxER4MZCpeVh+Kp/pgC/K2Ov hpaSLeYLZUkg+N0wC4Ga0Qq6UgMx/cTNuo7q6yN9h8R7bUebu5cPEBcq4cTSE1yAzG XaolljQFjxmkycxQ14XwpyNKq0/OWhD9o1qm0W9dJfcwt++M0/+061ckOYVZTZglYF NRnOQ1pp5uyTw== Received: by pali.im (Postfix) id 999277F6; Fri, 22 Oct 2021 16:22:44 +0200 (CEST) From: =?UTF-8?q?Pali=20Roh=C3=A1r?= To: Stefan Roese Cc: =?UTF-8?q?Marek=20Beh=C3=BAn?= , u-boot@lists.denx.de Subject: [PATCH 0/8] pci: pci_mvebu: Fix access to config space and PCIe Root Port Date: Fri, 22 Oct 2021 16:22:07 +0200 Message-Id: <20211022142215.26484-1-pali@kernel.org> X-Mailer: git-send-email 2.20.1 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean This patch series fixes access to config space and fixes issues with the mysterious "Memory controller" PCI device (which is PCIe Root Port). Tested on Armada 385 Turris Omnia device which has 3 mPCIe slots. PCIe Root Port device is available for each slot on separate bus and has PCI Bridge class code as required by PCIe base specifications. => pci 0 Scanning PCI devices on bus 0 BusDevFun VendorId DeviceId Device Class Sub-Class _____________________________________________________________ 00.00.00 0x11ab 0x6820 Bridge device 0x04 => pci 1 Scanning PCI devices on bus 1 BusDevFun VendorId DeviceId Device Class Sub-Class _____________________________________________________________ 01.00.00 0x168c 0x003c Network controller 0x80 => pci 2 Scanning PCI devices on bus 2 BusDevFun VendorId DeviceId Device Class Sub-Class _____________________________________________________________ 02.00.00 0x11ab 0x6820 Bridge device 0x04 => pci 3 Scanning PCI devices on bus 3 BusDevFun VendorId DeviceId Device Class Sub-Class _____________________________________________________________ 03.00.00 0x168c 0x003c Network controller 0x80 => pci 4 Scanning PCI devices on bus 4 BusDevFun VendorId DeviceId Device Class Sub-Class _____________________________________________________________ 04.00.00 0x11ab 0x6820 Bridge device 0x04 => pci 5 Scanning PCI devices on bus 5 BusDevFun VendorId DeviceId Device Class Sub-Class _____________________________________________________________ 05.00.00 0x168c 0x002e Network controller 0x80 => pci 6 No such bus => U-Boot command "pci display.b 0.0.0 0 200" will display config space of the first PCIe Root Port device with the Type 1 PCI header as required by PCIe base specification. => pci display.b 0.0.0 0 200 00000000: ab 11 20 68 07 00 10 00 04 00 04 06 00 00 01 00 00000010: 00 00 00 00 00 00 00 00 00 01 01 00 01 f1 00 00 00000020: 00 c0 20 c0 01 10 01 00 00 00 00 00 00 00 00 00 00000030: 10 f1 0f f1 40 00 00 00 00 00 00 00 00 01 00 00 00000040: 01 50 03 06 00 00 00 00 00 00 00 00 00 00 00 00 00000050: 05 60 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00000060: 10 00 42 00 80 80 00 00 00 20 00 00 12 ac 07 00 00000070: 00 00 11 10 00 00 00 00 00 00 40 00 00 00 00 00 00000080: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00000090: 02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 000000a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 000000b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 000000c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 000000d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 000000e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 000000f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00000100: 01 00 01 00 00 00 00 00 00 00 00 00 10 00 06 00 00000110: 00 00 00 00 00 20 00 00 00 00 00 00 01 00 00 4a 00000120: 04 00 00 01 00 01 08 01 02 80 00 00 00 00 00 00 00000130: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00000140: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00000150: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00000160: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00000170: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00000180: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00000190: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 000001a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 000001b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 000001c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 000001d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 000001e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 000001f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Pali Rohár (8): pci: pci_mvebu: Fix write_config() with PCI_SIZE_8 or PCI_SIZE_16 pci: pci_mvebu: Fix read_config() with PCI_SIZE_8 or PCI_SIZE_16 pci: pci_mvebu: Properly configure and use PCI Bridge (PCIe Root Port) pci: pci_mvebu: Remove unused functions pci: pci_mvebu: Fix place of link up detection pci: pci_mvebu: Do not automatically enable bus mastering on PCI Bridge pci: pci_mvebu: Setup PCI controller to Root Complex mode pci: pci_mvebu: Fix comment about driver class name drivers/pci/pci_mvebu.c | 275 +++++++++++++++++++++++++++++----------- 1 file changed, 202 insertions(+), 73 deletions(-) -- 2.20.1