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From: "Pali Rohár" <pali@kernel.org>
To: Stefan Roese <sr@denx.de>
Cc: "Marek Behún" <marek.behun@nic.cz>, u-boot@lists.denx.de
Subject: [PATCH 2/8] pci: pci_mvebu: Fix read_config() with PCI_SIZE_8 or PCI_SIZE_16
Date: Fri, 22 Oct 2021 16:22:09 +0200	[thread overview]
Message-ID: <20211022142215.26484-3-pali@kernel.org> (raw)
In-Reply-To: <20211022142215.26484-1-pali@kernel.org>

When reading 8 or 16 bits from config space, use appropriate readb() or
readw() calls. This ensures that PCIe controller does not read more bits
from endpoint card as asked by read_config() function.

Technically there should not be an issue with reading data from config
space which are not later used as there are no clear-by-read registers.
But it is better to use correct read operation based on requested size.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Marek Behún <marek.behun@nic.cz>
---
 drivers/pci/pci_mvebu.c | 17 +++++++++++++++--
 1 file changed, 15 insertions(+), 2 deletions(-)

diff --git a/drivers/pci/pci_mvebu.c b/drivers/pci/pci_mvebu.c
index 8175511514ab..3991086e0d29 100644
--- a/drivers/pci/pci_mvebu.c
+++ b/drivers/pci/pci_mvebu.c
@@ -184,9 +184,22 @@ static int mvebu_pcie_read_config(const struct udevice *bus, pci_dev_t bdf,
 	writel(PCIE_CONF_ADDR(bdf, offset), pcie->base + PCIE_CONF_ADDR_OFF);
 
 	/* read data */
-	data = readl(pcie->base + PCIE_CONF_DATA_OFF);
+	switch (size) {
+	case PCI_SIZE_8:
+		data = readb(pcie->base + PCIE_CONF_DATA_OFF + (offset & 3));
+		break;
+	case PCI_SIZE_16:
+		data = readw(pcie->base + PCIE_CONF_DATA_OFF + (offset & 2));
+		break;
+	case PCI_SIZE_32:
+		data = readl(pcie->base + PCIE_CONF_DATA_OFF);
+		break;
+	default:
+		return -EINVAL;
+	}
+
 	debug("(addr,size,val)=(0x%04x, %d, 0x%08x)\n", offset, size, data);
-	*valuep = pci_conv_32_to_size(data, offset, size);
+	*valuep = data;
 
 	return 0;
 }
-- 
2.20.1


  parent reply	other threads:[~2021-10-22 14:23 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-10-22 14:22 [PATCH 0/8] pci: pci_mvebu: Fix access to config space and PCIe Root Port Pali Rohár
2021-10-22 14:22 ` [PATCH 1/8] pci: pci_mvebu: Fix write_config() with PCI_SIZE_8 or PCI_SIZE_16 Pali Rohár
2021-11-02 10:44   ` Stefan Roese
2021-10-22 14:22 ` Pali Rohár [this message]
2021-11-02 10:45   ` [PATCH 2/8] pci: pci_mvebu: Fix read_config() " Stefan Roese
2021-10-22 14:22 ` [PATCH 3/8] pci: pci_mvebu: Properly configure and use PCI Bridge (PCIe Root Port) Pali Rohár
2021-11-02 10:47   ` Stefan Roese
2021-10-22 14:22 ` [PATCH 4/8] pci: pci_mvebu: Remove unused functions Pali Rohár
2021-11-02 10:47   ` Stefan Roese
2021-10-22 14:22 ` [PATCH 5/8] pci: pci_mvebu: Fix place of link up detection Pali Rohár
2021-11-02 10:50   ` Stefan Roese
2021-10-22 14:22 ` [PATCH 6/8] pci: pci_mvebu: Do not automatically enable bus mastering on PCI Bridge Pali Rohár
2021-11-02 10:50   ` Stefan Roese
2021-10-22 14:22 ` [PATCH 7/8] pci: pci_mvebu: Setup PCI controller to Root Complex mode Pali Rohár
2021-11-02 10:50   ` Stefan Roese
2021-10-22 14:22 ` [PATCH 8/8] pci: pci_mvebu: Fix comment about driver class name Pali Rohár
2021-11-02 10:50   ` Stefan Roese
2021-11-03  7:46 ` [PATCH 0/8] pci: pci_mvebu: Fix access to config space and PCIe Root Port Stefan Roese

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