From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 37396C433F5 for ; Fri, 22 Oct 2021 14:23:55 +0000 (UTC) Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id B00DB60E96 for ; Fri, 22 Oct 2021 14:23:54 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org B00DB60E96 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=kernel.org Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=lists.denx.de Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 9869D834F4; Fri, 22 Oct 2021 16:23:34 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=kernel.org header.i=@kernel.org header.b="dYNMf1iv"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 95D0883529; Fri, 22 Oct 2021 16:23:10 +0200 (CEST) Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 489988353B for ; Fri, 22 Oct 2021 16:22:52 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=pali@kernel.org Received: by mail.kernel.org (Postfix) with ESMTPSA id 2CCA360E96; Fri, 22 Oct 2021 14:22:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1634912568; bh=L7oaZJbEbe79dAkwACQplhOBH/uonIboBKZXLd09YZo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=dYNMf1ivmR9+P7yWdjhg0SdmKobnu7YGa90LwSwoStjV2kDFQMyVqVVwgQHHlGnnA GZHelV9rLKCAnmL7MOAy7xuU+GZFDc6rprJkgFaUT6h1iJbiCBSwir9H0MJimRauPt JRBPlWqwQO7w3N4vJJODh5cBaKici6mmCMQVyxHuEiNZjLYYQDFlDK7xiqKxJ/utUx wwss9x6lFbEtfs9na6wVKOkEkjt9xBvZpsXZqFVXynUHEnJ9z5Sk48CWRpDcxTCUVs 2i1seXb7ycKsbR/iGW5xJ9fnLcGTuXL+SnON0izysCDdnL2l1VoQW0rFkrpcQZoSic xbjLy2/5ktcrA== Received: by pali.im (Postfix) id 219CAE93; Fri, 22 Oct 2021 16:22:46 +0200 (CEST) From: =?UTF-8?q?Pali=20Roh=C3=A1r?= To: Stefan Roese Cc: =?UTF-8?q?Marek=20Beh=C3=BAn?= , u-boot@lists.denx.de Subject: [PATCH 6/8] pci: pci_mvebu: Do not automatically enable bus mastering on PCI Bridge Date: Fri, 22 Oct 2021 16:22:13 +0200 Message-Id: <20211022142215.26484-7-pali@kernel.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20211022142215.26484-1-pali@kernel.org> References: <20211022142215.26484-1-pali@kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean Now that PCI Bridge is working, U-Boot's CONFIG_PCI_PNP code automatically enables memory access and bus mastering when it is needed. So do not prematurely enable memory access and bus mastering. Signed-off-by: Pali Rohár Reviewed-by: Marek Behún --- drivers/pci/pci_mvebu.c | 8 -------- 1 file changed, 8 deletions(-) diff --git a/drivers/pci/pci_mvebu.c b/drivers/pci/pci_mvebu.c index 40b8a57bbe1e..e43fa12d3819 100644 --- a/drivers/pci/pci_mvebu.c +++ b/drivers/pci/pci_mvebu.c @@ -451,14 +451,6 @@ static int mvebu_pcie_probe(struct udevice *dev) /* Setup windows and configure host bridge */ mvebu_pcie_setup_wins(pcie); - /* Master + slave enable. */ - reg = readl(pcie->base + PCIE_CMD_OFF); - reg |= PCI_COMMAND_MEMORY; - reg |= PCI_COMMAND_IO; - reg |= PCI_COMMAND_MASTER; - reg |= BIT(10); /* disable interrupts */ - writel(reg, pcie->base + PCIE_CMD_OFF); - /* PCI memory space */ pci_set_region(hose->regions + 0, pcie->mem.start, pcie->mem.start, PCIE_MEM_SIZE, PCI_REGION_MEM); -- 2.20.1