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From: "Pali Rohár" <pali@kernel.org>
To: Stefan Roese <sr@denx.de>
Cc: "Marek Behún" <marek.behun@nic.cz>, u-boot@lists.denx.de
Subject: [PATCH 7/8] pci: pci_mvebu: Setup PCI controller to Root Complex mode
Date: Fri, 22 Oct 2021 16:22:14 +0200	[thread overview]
Message-ID: <20211022142215.26484-8-pali@kernel.org> (raw)
In-Reply-To: <20211022142215.26484-1-pali@kernel.org>

Root Complex should be the default mode, let's set it explicitly.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Marek Behún <marek.behun@nic.cz>
---
 drivers/pci/pci_mvebu.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/pci/pci_mvebu.c b/drivers/pci/pci_mvebu.c
index e43fa12d3819..b0c673d8c472 100644
--- a/drivers/pci/pci_mvebu.c
+++ b/drivers/pci/pci_mvebu.c
@@ -62,6 +62,7 @@ DECLARE_GLOBAL_DATA_PTR;
 #define  PCIE_MASK_ENABLE_INTS          (0xf << 24)
 #define PCIE_CTRL_OFF			0x1a00
 #define  PCIE_CTRL_X1_MODE		BIT(0)
+#define  PCIE_CTRL_RC_MODE		BIT(1)
 #define PCIE_STAT_OFF			0x1a04
 #define  PCIE_STAT_BUS                  (0xff << 8)
 #define  PCIE_STAT_DEV                  (0x1f << 16)
@@ -373,6 +374,11 @@ static int mvebu_pcie_probe(struct udevice *dev)
 	struct pci_controller *hose = dev_get_uclass_priv(ctlr);
 	u32 reg;
 
+	/* Setup PCIe controller to Root Complex mode */
+	reg = readl(pcie->base + PCIE_CTRL_OFF);
+	reg |= PCIE_CTRL_RC_MODE;
+	writel(reg, pcie->base + PCIE_CTRL_OFF);
+
 	/*
 	 * Change Class Code of PCI Bridge device to PCI Bridge (0x600400)
 	 * because default value is Memory controller (0x508000) which
-- 
2.20.1


  parent reply	other threads:[~2021-10-22 14:24 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-10-22 14:22 [PATCH 0/8] pci: pci_mvebu: Fix access to config space and PCIe Root Port Pali Rohár
2021-10-22 14:22 ` [PATCH 1/8] pci: pci_mvebu: Fix write_config() with PCI_SIZE_8 or PCI_SIZE_16 Pali Rohár
2021-11-02 10:44   ` Stefan Roese
2021-10-22 14:22 ` [PATCH 2/8] pci: pci_mvebu: Fix read_config() " Pali Rohár
2021-11-02 10:45   ` Stefan Roese
2021-10-22 14:22 ` [PATCH 3/8] pci: pci_mvebu: Properly configure and use PCI Bridge (PCIe Root Port) Pali Rohár
2021-11-02 10:47   ` Stefan Roese
2021-10-22 14:22 ` [PATCH 4/8] pci: pci_mvebu: Remove unused functions Pali Rohár
2021-11-02 10:47   ` Stefan Roese
2021-10-22 14:22 ` [PATCH 5/8] pci: pci_mvebu: Fix place of link up detection Pali Rohár
2021-11-02 10:50   ` Stefan Roese
2021-10-22 14:22 ` [PATCH 6/8] pci: pci_mvebu: Do not automatically enable bus mastering on PCI Bridge Pali Rohár
2021-11-02 10:50   ` Stefan Roese
2021-10-22 14:22 ` Pali Rohár [this message]
2021-11-02 10:50   ` [PATCH 7/8] pci: pci_mvebu: Setup PCI controller to Root Complex mode Stefan Roese
2021-10-22 14:22 ` [PATCH 8/8] pci: pci_mvebu: Fix comment about driver class name Pali Rohár
2021-11-02 10:50   ` Stefan Roese
2021-11-03  7:46 ` [PATCH 0/8] pci: pci_mvebu: Fix access to config space and PCIe Root Port Stefan Roese

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