From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9E0D0C433EF for ; Sun, 7 Nov 2021 15:11:21 +0000 (UTC) Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id F0D6061076 for ; Sun, 7 Nov 2021 15:11:20 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org F0D6061076 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=lists.denx.de Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id A0D8A837E6; Sun, 7 Nov 2021 16:11:14 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id 04CE7837DE; Sun, 7 Nov 2021 16:09:24 +0100 (CET) Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 6896E837E6 for ; Sun, 7 Nov 2021 16:09:17 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=sin.hui.kho@intel.com X-IronPort-AV: E=McAfee;i="6200,9189,10160"; a="295551215" X-IronPort-AV: E=Sophos;i="5.87,216,1631602800"; d="scan'208";a="295551215" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Nov 2021 07:09:15 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.87,216,1631602800"; d="scan'208";a="587434366" Received: from pglc00493.png.intel.com ([10.221.239.176]) by fmsmga002.fm.intel.com with ESMTP; 07 Nov 2021 07:09:13 -0800 From: sin.hui.kho@intel.com To: u-boot@lists.denx.de Cc: Simon Goldschmidt , Marek Vasut , Tien Fong Chee , Kok Kiang Hea , Westergteen Dalon , Cozart Sue , Sin Hui Kho Subject: [PATCH 3/3] arm: socfpga: arria10: Enable double peripheral RBF configuration Date: Sun, 7 Nov 2021 23:08:56 +0800 Message-Id: <20211107150856.19256-3-sin.hui.kho@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211107150856.19256-1-sin.hui.kho@intel.com> References: <20211107150856.19256-1-sin.hui.kho@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Mailman-Approved-At: Sun, 07 Nov 2021 16:11:05 +0100 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean From: Tien Fong Chee Double peripheral RBF configuration are needed on some devices or boards to stabilize the IO configuration system. Signed-off-by: Tien Fong Chee Signed-off-by: Sin Hui Kho --- arch/arm/mach-socfpga/include/mach/misc.h | 2 ++ arch/arm/mach-socfpga/misc_arria10.c | 36 +++++++++++++++++++++++ arch/arm/mach-socfpga/spl_a10.c | 14 +++++++++ drivers/fpga/socfpga_arria10.c | 3 +- 4 files changed, 54 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-socfpga/include/mach/misc.h b/arch/arm/mach-socfpga/include/mach/misc.h index 74e8e2590f..8460acb00d 100644 --- a/arch/arm/mach-socfpga/include/mach/misc.h +++ b/arch/arm/mach-socfpga/include/mach/misc.h @@ -45,7 +45,9 @@ int is_fpga_config_ready(void); #endif void do_bridge_reset(int enable, unsigned int mask); +void force_periph_program(unsigned int status); bool is_regular_boot_valid(void); +bool is_periph_program_force(void); void set_regular_boot(unsigned int status); void socfpga_pl310_clear(void); void socfpga_get_managers_addr(void); diff --git a/arch/arm/mach-socfpga/misc_arria10.c b/arch/arm/mach-socfpga/misc_arria10.c index 634e63ed42..0ed2adfd84 100644 --- a/arch/arm/mach-socfpga/misc_arria10.c +++ b/arch/arm/mach-socfpga/misc_arria10.c @@ -32,6 +32,7 @@ #define PINMUX_UART1_TX_SHARED_IO_OFFSET_Q4_3 0x98 #define REGULAR_BOOT_MAGIC 0xd15ea5e +#define PERIPH_RBF_PROG_FORCE 0x50455249 #define QSPI_S25FL_SOFT_RESET_COMMAND 0x00f0ff82 #define QSPI_N25_SOFT_RESET_COMMAND 0x00000001 @@ -131,6 +132,41 @@ void do_bridge_reset(int enable, unsigned int mask) socfpga_bridges_reset(); } +/* + * This function set/unset flag with number "0x50455249" to + * handoff register isw_handoff[7] - 0xffd0624c + * This flag is used to force periph RBF program regardless FPGA status + * and double periph RBF config are needed on some devices or boards to + * stabilize the IO config system. + */ +void force_periph_program(unsigned int status) +{ + if (status) + writel(PERIPH_RBF_PROG_FORCE, socfpga_get_sysmgr_addr() + + SYSMGR_A10_ISW_HANDOFF_BASE + SYSMGR_A10_ISW_HANDOFF_7); + else + writel(0, socfpga_get_sysmgr_addr() + + SYSMGR_A10_ISW_HANDOFF_BASE + SYSMGR_A10_ISW_HANDOFF_7); +} + +/* + * This function is used to check whether + * handoff register isw_handoff[7] contains + * flag for forcing the periph RBF program "0x50455249". + */ +bool is_periph_program_force(void) +{ + unsigned int status; + + status = readl(socfpga_get_sysmgr_addr() + + SYSMGR_A10_ISW_HANDOFF_BASE + SYSMGR_A10_ISW_HANDOFF_7); + + if (status == PERIPH_RBF_PROG_FORCE) + return true; + else + return false; +} + /* * This function set/unset magic number "0xd15ea5e" to * handoff register isw_handoff[7] - 0xffd0624c diff --git a/arch/arm/mach-socfpga/spl_a10.c b/arch/arm/mach-socfpga/spl_a10.c index 6450f75058..d2f454cd24 100644 --- a/arch/arm/mach-socfpga/spl_a10.c +++ b/arch/arm/mach-socfpga/spl_a10.c @@ -133,6 +133,20 @@ void spl_board_init(void) } else if (!is_fpgamgr_early_user_mode()) { /* Program IOSSM(early IO release) or full FPGA */ fpgamgr_program(buf, FPGA_BUFSIZ, 0); + + /* Skipping double program for combined RBF */ + if (!is_fpgamgr_user_mode()) { + /* + * Expect FPGA entered early user mode, so + * the flag is set to re-program IOSSM + */ + force_periph_program(true); + + /* Re-program IOSSM to stabilize IO system */ + fpgamgr_program(buf, FPGA_BUFSIZ, 0); + + force_periph_program(false); + } } /* If the IOSSM/full FPGA is already loaded, start DDR */ diff --git a/drivers/fpga/socfpga_arria10.c b/drivers/fpga/socfpga_arria10.c index b992e6f080..798e3a3f90 100644 --- a/drivers/fpga/socfpga_arria10.c +++ b/drivers/fpga/socfpga_arria10.c @@ -604,7 +604,8 @@ static int first_loading_rbf_to_buffer(struct udevice *dev, if (strstr(uname, "fpga-periph") && (!is_fpgamgr_early_user_mode() || - is_fpgamgr_user_mode())) { + is_fpgamgr_user_mode() || + is_periph_program_force())) { fpga_node_name = uname; printf("FPGA: Start to program "); printf("peripheral/full bitstream ...\n"); -- 2.25.1