From: "Pali Rohár" <pali@kernel.org>
To: Stefan Roese <sr@denx.de>, Simon Glass <sjg@chromium.org>,
Bin Meng <bmeng.cn@gmail.com>
Cc: u-boot@lists.denx.de
Subject: [PATCH] pci: Fix register for determining type of IO base address
Date: Thu, 25 Nov 2021 11:30:58 +0100 [thread overview]
Message-ID: <20211125103058.23739-1-pali@kernel.org> (raw)
Function dm_pciauto_prescan_setup_bridge() configures base address
registers, therefore it should read type of IO from base address registers
(and not from limit address registers).
Note that base and limit address registers should have same type, so this
change is just usage correction and has no functional change on correctly
working hardware.
Fixes: 8e85f36a8fab ("pci: Fix configuring io/memory base and limit registers of PCI bridges")
Signed-off-by: Pali Rohár <pali@kernel.org>
---
drivers/pci/pci_auto.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/pci/pci_auto.c b/drivers/pci/pci_auto.c
index 5af4ee6e56df..7e6ee54be087 100644
--- a/drivers/pci/pci_auto.c
+++ b/drivers/pci/pci_auto.c
@@ -197,7 +197,7 @@ void dm_pciauto_prescan_setup_bridge(struct udevice *dev, int sub_bus)
dm_pci_read_config16(dev, PCI_COMMAND, &cmdstat);
dm_pci_read_config16(dev, PCI_PREF_MEMORY_BASE, &prefechable_64);
prefechable_64 &= PCI_PREF_RANGE_TYPE_MASK;
- dm_pci_read_config8(dev, PCI_IO_LIMIT, &io_32);
+ dm_pci_read_config8(dev, PCI_IO_BASE, &io_32);
io_32 &= PCI_IO_RANGE_TYPE_MASK;
/* Configure bus number registers */
--
2.20.1
next reply other threads:[~2021-11-25 10:31 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-11-25 10:30 Pali Rohár [this message]
2021-11-30 6:06 ` [PATCH] pci: Fix register for determining type of IO base address Stefan Roese
2022-01-13 1:51 ` Tom Rini
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