From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3F9BBC433EF for ; Sun, 28 Nov 2021 11:33:17 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 044AB83022; Sun, 28 Nov 2021 12:33:15 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="f6vcOjMe"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 3036580F6F; Sun, 28 Nov 2021 12:33:00 +0100 (CET) Received: from mail-wm1-x32e.google.com (mail-wm1-x32e.google.com [IPv6:2a00:1450:4864:20::32e]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id CDFD980F6F for ; Sun, 28 Nov 2021 12:32:54 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=atomar25opensource@gmail.com Received: by mail-wm1-x32e.google.com with SMTP id o29so12204734wms.2 for ; Sun, 28 Nov 2021 03:32:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Eztkhr7tWYv5N7Leb7Xh1oBY454LWcxMr5BM+Yp8cLU=; b=f6vcOjMeczpgvYzleEa7jR/2E0yN8ZeLdZ5wCiVLbhkzCXbvxOLFtY3wb4BQNmK6Vc 8vEW35wfUoKtm9m01Cv1R9vtf4SpyoiDpmxMoiyAoynPBoQnCca6GQhYFrgKjRIzO8d/ TzhR5h0/+4kaSYHDnYzUyOKRXB/I2q+hYzh1WfRRNkRIrNoKq8z6BxU7dA/+du0d3H09 BcauRgYhslqT1+xEdr0se6HtjYFUl7tnQdz7wgYqFJCLkZXyr/1OX5BNdOsAH2Qqxwhb y5h8qzr2gLuXlm9Mh8zIU+d5BWanDV2CmctpSOpMusIKx/AQCtw1S1zY2lzRUmf4+e1M a4Wg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Eztkhr7tWYv5N7Leb7Xh1oBY454LWcxMr5BM+Yp8cLU=; b=7UDwQzFJGy5h38+nGfrMLVpjOI67bxPbnM1RwfZW6fEoaP029Y03WvSF57ymK+Q5cp gvbOPyprjP8b8+OqbZJAv5WHiMQDLoNYIM5JxS2bGaHCMxoV7yye8AbBJ2lannnIvluC khyxsdaKl/ArJ6H6xCkaHkODPsHJcP8EQOA9ULOSoJYCY/YWFMC/sFHEscD2tGfZPLIj vH1cSZBN3X1W92XdcVnD8zlugHGLfbyjmV9EW5YUc0yTtrNU3JoM3dy6mTE0/P85VvJL lCTsQVCfkIFt4tQUkSd3VVe58MP7sZA3lzu69ySEmSD6dWePjXAVQuo71yuCdf8D7WA+ n0VA== X-Gm-Message-State: AOAM530HM9tjTf15idaB0nYSQzkOOxxeE+1O3jwJlIV36upqMs2sp4xd bPv5GfWe5F/fgYraJiALtZiYip4OmdVB X-Google-Smtp-Source: ABdhPJwSfO1txuqOY6dpTvK2gePVtGhWeCAGhubJ68hpTGPBmKJ8dwzva1MVy2/c30ZhzOrGUGP9/g== X-Received: by 2002:a05:600c:282:: with SMTP id 2mr29123395wmk.91.1638099174064; Sun, 28 Nov 2021 03:32:54 -0800 (PST) Received: from amit-VirtualBox.world.mentorg.com (nat-inn.mentorg.com. [192.94.34.34]) by smtp.gmail.com with ESMTPSA id b6sm17335285wmq.45.2021.11.28.03.32.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 28 Nov 2021 03:32:53 -0800 (PST) From: Amit Singh Tomar To: u-boot@lists.denx.de Cc: andre.przywara@arm.com, manivannan.sadhasivam@linaro.org, joe.hershberger@ni.com, jh80.chung@samsung.com, Amit Singh Tomar Subject: [PATCH v4 2/6] clk: actions: Add SD/MMC clocks Date: Sun, 28 Nov 2021 17:02:21 +0530 Message-Id: <20211128113225.3992-3-atomar25opensource@gmail.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20211128113225.3992-1-atomar25opensource@gmail.com> References: <20211128113225.3992-1-atomar25opensource@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.37 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean From: Amit Singh Tomar This commit adds SD/MMC clocks, and provides .set/get_rate callbacks for SD/MMC device present on Actions OWL S700 SoCs. Signed-off-by: Amit Singh Tomar --- Changes since v3: * No change. Changes since v2: * Fixed the weird div assignment. * Moved the clock bit for SD from header file to driver file. * Removed "< 0" part while comparing unsigned. Changes since previous version: * Removed rate *= 2 as this just overclocks. * Separated the divide by 128 bit from divider value. * Provided the separate routine to get sd parent rate based on bit 9. * Removed unnecessary initialization. --- drivers/clk/owl/clk_owl.c | 73 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 73 insertions(+) diff --git a/drivers/clk/owl/clk_owl.c b/drivers/clk/owl/clk_owl.c index f78e5fa3f08d..678fdd5a4540 100644 --- a/drivers/clk/owl/clk_owl.c +++ b/drivers/clk/owl/clk_owl.c @@ -20,6 +20,8 @@ #include #include +#define CMU_DEVCLKEN0_SD0 BIT(22) + void owl_clk_init(struct owl_clk_priv *priv) { u32 bus_clk = 0, core_pll, dev_pll; @@ -92,6 +94,9 @@ int owl_clk_enable(struct clk *clk) setbits_le32(priv->base + CMU_DEVCLKEN1, CMU_DEVCLKEN1_ETH); setbits_le32(priv->base + CMU_ETHERNETPLL, 5); break; + case CLK_SD0: + setbits_le32(priv->base + CMU_DEVCLKEN0, CMU_DEVCLKEN0_SD0); + break; default: return -EINVAL; } @@ -121,6 +126,9 @@ int owl_clk_disable(struct clk *clk) case CLK_ETHERNET: clrbits_le32(priv->base + CMU_DEVCLKEN1, CMU_DEVCLKEN1_ETH); break; + case CLK_SD0: + clrbits_le32(priv->base + CMU_DEVCLKEN0, CMU_DEVCLKEN0_SD0); + break; default: return -EINVAL; } @@ -128,11 +136,72 @@ int owl_clk_disable(struct clk *clk) return 0; } +static ulong get_sd_parent_rate(struct owl_clk_priv *priv, u32 dev_index) +{ + ulong rate; + u32 reg; + + reg = readl(priv->base + (CMU_SD0CLK + dev_index * 0x4)); + /* Clock output of DEV/NAND_PLL + * Range: 48M ~ 756M + * Frequency= PLLCLK * 6 + */ + if (reg & 0x200) + rate = readl(priv->base + CMU_NANDPLL) & 0x7f; + else + rate = readl(priv->base + CMU_DEVPLL) & 0x7f; + + rate *= 6000000; + + return rate; +} + +static ulong owl_get_sd_clk_rate(struct owl_clk_priv *priv, int sd_index) +{ + uint div, val; + ulong parent_rate = get_sd_parent_rate(priv, sd_index); + + val = readl(priv->base + (CMU_SD0CLK + sd_index * 0x4)); + div = (val & 0x1f) + 1; + + return (parent_rate / div); +} + +static ulong owl_set_sd_clk_rate(struct owl_clk_priv *priv, ulong rate, + int sd_index) +{ + uint div, val; + ulong parent_rate = get_sd_parent_rate(priv, sd_index); + + if (rate == 0) + return rate; + + div = (parent_rate / rate); + + val = readl(priv->base + (CMU_SD0CLK + sd_index * 0x4)); + /* Bits 4..0 is used to program div value and bit 8 to enable + * divide by 128 circuit + */ + val &= ~0x11f; + if (div >= 128) { + div = div / 128; + val |= 0x100; /* enable divide by 128 circuit */ + } + val |= ((div - 1) & 0x1f); + writel(val, priv->base + (CMU_SD0CLK + sd_index * 0x4)); + + return owl_get_sd_clk_rate(priv, 0); +} + static ulong owl_clk_get_rate(struct clk *clk) { + struct owl_clk_priv *priv = dev_get_priv(clk->dev); ulong rate; switch (clk->id) { + case CLK_SD0: + rate = owl_get_sd_clk_rate(priv, 0); + break; default: return -ENOENT; } @@ -142,9 +211,13 @@ static ulong owl_clk_get_rate(struct clk *clk) static ulong owl_clk_set_rate(struct clk *clk, ulong rate) { + struct owl_clk_priv *priv = dev_get_priv(clk->dev); ulong new_rate; switch (clk->id) { + case CLK_SD0: + new_rate = owl_set_sd_clk_rate(priv, rate, 0); + break; default: return -ENOENT; } -- 2.27.0