From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 79606C433F5 for ; Wed, 15 Dec 2021 03:02:08 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 8B27B83033; Wed, 15 Dec 2021 04:01:44 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="YqV3WpVP"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 33D058069D; Wed, 15 Dec 2021 03:58:53 +0100 (CET) Received: from mail-pg1-x534.google.com (mail-pg1-x534.google.com [IPv6:2607:f8b0:4864:20::534]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 7BB3E82FE2 for ; Wed, 15 Dec 2021 03:58:47 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=stanley.chuys@gmail.com Received: by mail-pg1-x534.google.com with SMTP id y9so5747740pgj.5 for ; Tue, 14 Dec 2021 18:58:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=NZsDJlG+MJZBEfXFoM6d9xWu+21H+DyOVf6kY8BagIw=; b=YqV3WpVPjTq0ARh2BCzD1IUg/bQA7/SnFNAiyY1r+rDQNso3AHsDrqrEzW/sUaXsTc koKdZmCCzOhFtjf+cqMMV3m19jbEpdzEGBhk3eWDaDDiKtnuQLUK5VASK3891k+pmLf7 PcjX35ZAYvN0kKNA+B3SO7pjUoCddXOV4X23CxVCHSzSy3iBNUb4RbyYX1LQezOuQkID ZKHAEAq+H6a4VrIE6UrYD6/NpJhWDh6slJ7VWkkUKwh2lMIR9AqNkNhzRSa8S5zV7BES eLnXRxh5MgE+ndx/0/SXmnxJZZFXe3RFNCmokN33JvkyP7YHyWKMHM6y06fEgZKh6Svg FSJw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=NZsDJlG+MJZBEfXFoM6d9xWu+21H+DyOVf6kY8BagIw=; b=kTBxpJLcMUO+ehoIHom26t2GjCpzxCmniOoFjtu6VXLS0YJUuQK1iUastemk1+h5D+ FoQXlEZaZOqDpBsTt0+qtZIvCdrZq5xT6WdknRycaw0OVqMHih4sP8GqHQ5UCfCjHUuS JffnddnIKAnWFIPxipW9zZbOrHvoMkknCe7UipovN/QM6ft3SUuWU0iqYrtl76LlAPt/ 46iCURfVZEqcYxyYNhKD2inHVZ+PZTnN5Pvmv8xrhM82HBPi+J8cumVHEhkI+xFZj/Oz Pn3bR3SXKvQ/dOvgu5UfOX/r9z2tDriRXqWw5V9b0Ci/uP1C9ZMAo/Z0jVmZfHX134bW u6bA== X-Gm-Message-State: AOAM530NVyH/CB8Dir04GFwhA9EGNoostfYRWve6O5yzlqxG5Fwce+B9 mWU2utc/o6iSppq0KFfckjQ= X-Google-Smtp-Source: ABdhPJyO3QaTEhONCQiW/EvYmC3hfuwFnpFpPGkHox6Lzz59fUeyS+hnwvNIc4N27YU3W6vRulAtNA== X-Received: by 2002:a63:dc0b:: with SMTP id s11mr6406806pgg.272.1639537125849; Tue, 14 Dec 2021 18:58:45 -0800 (PST) Received: from cs20-buildserver.lan ([180.217.149.17]) by smtp.gmail.com with ESMTPSA id q18sm437413pfn.83.2021.12.14.18.58.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Dec 2021 18:58:45 -0800 (PST) From: Stanley Chu X-Google-Original-From: Stanley Chu To: lukma@denx.de, jagan@amarulasolutions.com, andre.przywara@arm.com, festevam@denx.de, narmstrong@baylibre.com, pbrobinson@gmail.com, tharvey@gateworks.com, christianshewitt@gmail.com, lokeshvutla@ti.com, sjg@chromium.org, sr@denx.de, michal.simek@xilinx.com, hs@denx.de, weijie.gao@mediatek.com, hannes.schmelzer@br-automation.com, harm.berntsen@nedap.com, sebastian.reichel@collabora.com, stephan@gerhold.net, fangyuanseu@gmail.com, kettenis@openbsd.org, seanga2@gmail.com, dsankouski@gmail.com, vabhav.sharma@nxp.com, bmeng.cn@gmail.com, patrick@blueri.se, samuel@sholland.org, giulio.benetti@benettiengineering.com, mr.bossman075@gmail.com, yschu@nuvoton.com, kwliu@nuvoton.com, ctcchien@nuvoton.com, avifishman70@gmail.com, tmaimon77@gmail.com Cc: u-boot@lists.denx.de, openbmc@lists.ozlabs.org Subject: [PATCH v1 3/9] timer: npcm: Add NPCM timer support Date: Wed, 15 Dec 2021 10:57:54 +0800 Message-Id: <20211215025800.26918-4-yschu@nuvoton.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20211215025800.26918-1-yschu@nuvoton.com> References: <20211215025800.26918-1-yschu@nuvoton.com> X-Mailman-Approved-At: Wed, 15 Dec 2021 04:01:29 +0100 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.38 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean Add Nuvoton BMC NPCM7xx/NPCM8xx timer driver. Signed-off-by: Stanley Chu --- drivers/timer/Kconfig | 7 ++++ drivers/timer/Makefile | 1 + drivers/timer/npcm_timer.c | 82 ++++++++++++++++++++++++++++++++++++++ 3 files changed, 90 insertions(+) create mode 100644 drivers/timer/npcm_timer.c diff --git a/drivers/timer/Kconfig b/drivers/timer/Kconfig index 8913142654..c17bc5b8b9 100644 --- a/drivers/timer/Kconfig +++ b/drivers/timer/Kconfig @@ -234,4 +234,11 @@ config IMX_GPT_TIMER Select this to enable support for the timer found on NXP i.MX devices. +config NPCM_TIMER + bool "Nuvoton NPCM timer support" + depends on TIMER + help + Select this to enable support for the timer found on + Nuvoton NPCM devices. + endmenu diff --git a/drivers/timer/Makefile b/drivers/timer/Makefile index e2bd530eb0..d6f04f1cf4 100644 --- a/drivers/timer/Makefile +++ b/drivers/timer/Makefile @@ -26,3 +26,4 @@ obj-$(CONFIG_X86_TSC_TIMER) += tsc_timer.o obj-$(CONFIG_MTK_TIMER) += mtk_timer.o obj-$(CONFIG_MCHP_PIT64B_TIMER) += mchp-pit64b-timer.o obj-$(CONFIG_IMX_GPT_TIMER) += imx-gpt-timer.o +obj-$(CONFIG_NPCM_TIMER) += npcm_timer.o diff --git a/drivers/timer/npcm_timer.c b/drivers/timer/npcm_timer.c new file mode 100644 index 0000000000..499c1003ff --- /dev/null +++ b/drivers/timer/npcm_timer.c @@ -0,0 +1,82 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2021 Nuvoton Technology. + */ + +#include +#include +#include +#include + +#define NPCM_CLOCK_RATE 1000000 +#define NPCM_TIMER_INIT_VAL 0xFFFFFFFF + +/* Register offsets */ +#define TCR0 0x0 +#define TICR0 0x8 +#define TDR0 0x10 + +/* TCR fields */ +#define TCR_MODE_PERIODIC BIT(27) +#define TCR_EN BIT(30) +#define TCR_PRESCALE_25 (25 - 1) + +struct npcm_timer_priv { + void __iomem *base; +}; + +static u64 npcm_timer_get_count(struct udevice *dev) +{ + struct npcm_timer_priv *priv = dev_get_priv(dev); + u32 val; + + val = NPCM_TIMER_INIT_VAL - readl(priv->base + TDR0); + + return timer_conv_64(val); +} + +static int npcm_timer_probe(struct udevice *dev) +{ + struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev); + struct npcm_timer_priv *priv = dev_get_priv(dev); + + priv->base = dev_read_addr_ptr(dev); + if (!priv->base) + return -ENOENT; + uc_priv->clock_rate = NPCM_CLOCK_RATE; + + writel(0, priv->base + TCR0); + writel(NPCM_TIMER_INIT_VAL, priv->base + TICR0); + + /* + * Configure timer and start + * periodic mode + * input clock freq = 25Mhz + * prescale = 25 + * clock rate = 25Mhz/25 = 1Mhz + */ + writel(TCR_EN | TCR_MODE_PERIODIC | TCR_PRESCALE_25, + priv->base + TCR0); + + return 0; +} + +static const struct timer_ops npcm_timer_ops = { + .get_count = npcm_timer_get_count, +}; + +static const struct udevice_id npcm_timer_ids[] = { + { .compatible = "nuvoton,npcm845-timer" }, + { .compatible = "nuvoton,npcm750-timer" }, + {} +}; + +U_BOOT_DRIVER(npcm_timer) = { + .name = "npcm_timer", + .id = UCLASS_TIMER, + .of_match = npcm_timer_ids, + .priv_auto = sizeof(struct npcm_timer_priv), + .probe = npcm_timer_probe, + .ops = &npcm_timer_ops, + .flags = DM_FLAG_PRE_RELOC, +}; -- 2.17.1